公开(公告)号：US20240164115A1

公开(公告)日：2024-05-16

申请号：US18504760

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Minsu SEOL ,  Yunseong LEE ,  Dongmin KIM ,  Sanghyun JO ,  Dukhyun CHOE

IPC: H10B53/30 ,  H01L21/28 ,  H01L29/04 ,  H01L29/51

CPC classification number: H10B53/30 ,  H01L29/045 ,  H01L29/40111 ,  H01L29/516

Abstract: Provided are a semiconductor device including a ferroelectric and an electronic apparatus including the semiconductor device. The semiconductor device includes a semiconductor layer, an electrode apart from the semiconductor layer, and a ferroelectric layer arranged between the semiconductor layer and the electrode. The ferroelectric layer includes a plurality of crystal grains, each of which having a first crystal orientation aligned within an angle range with respect to a first direction and having a second crystal orientation aligned within an angle range with respect to a second direction that is different from the first direction.

公开(公告)号：US20240113127A1

公开(公告)日：2024-04-04

申请号：US18529505

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L27/12 ,  G06N3/063 ,  G06N3/08

CPC classification number: H01L27/1207 ,  G06N3/063 ,  G06N3/08

Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

公开(公告)号：US20240072151A1

公开(公告)日：2024-02-29

申请号：US18502545

申请日：2023-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/78391

Abstract: Provided is a semiconductor device including a substrate on which a channel layer is provided, an insulation layer provided on the substrate, a ferroelectric layer provided on the insulation layer, a fixed charge region provided in the ferroelectric layer and containing charges of a predetermined polarity, and a gate provided on the ferroelectric layer. An absolute value of a charge density in the fixed charge region is greater than 0 and less than 5 μC/cm2.

公开(公告)号：US20240038891A1

公开(公告)日：2024-02-01

申请号：US18487275

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Hyangsook LEE

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/401 ,  H01L29/516

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20230328999A1

公开(公告)日：2023-10-12

申请号：US18332972

申请日：2023-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/66 ,  G11C11/22 ,  H01L21/28

CPC classification number: H10B51/30 ,  H01L29/78391 ,  H01L29/6684 ,  G11C11/223 ,  H01L29/40111 ,  G06N3/065

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

公开(公告)号：US20220068704A1

公开(公告)日：2022-03-03

申请号：US17411467

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20210313439A1

公开(公告)日：2021-10-07

申请号：US17119337

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein is an electronic device including: a lower gate electrode; a ferroelectric layer covering the lower gate electrode; a first insertion layer covering the ferroelectric layer and including a dielectric material; a channel layer provided on the first insertion layer, at a position corresponding to the lower gate electrode, the channel layer including an oxide semiconductor material; and a source electrode and a drain electrode formed to be electrically connected to both ends of the channel layer, respectively.

公开(公告)号：US20210098596A1

公开(公告)日：2021-04-01

申请号：US17036469

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Jinseong HEO ,  Hyangsook LEE ,  Sangwook KIM ,  Yunseong LEE

IPC: H01L29/51 ,  H01L21/02 ,  H01L49/02

Abstract: Disclosed herein is a thin film structure, including a first conductive layer on a dielectric layer including a plurality of layers. Each of the plurality of layers includes a dopant layer containing a dopant A and a HfO2 layer to form a compound of HfxA1-xOz (0

公开(公告)号：US20200303385A1

公开(公告)日：2020-09-24

申请号：US16893888

申请日：2020-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  G11C11/22 ,  H01L21/28

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

公开(公告)号：US20200176610A1

公开(公告)日：2020-06-04

申请号：US16682380

申请日：2019-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Sangwook KIM ,  Sanghyun JO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.