公开(公告)号：US10026872B2

公开(公告)日：2018-07-17

申请号：US15173661

申请日：2016-06-05

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/44 ,  H01L33/12 ,  H01L29/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/38 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20

Abstract: A solution for fabricating a device is described. The solution can include fabricating a heterostructure for the device, which includes at least one stress controlling layer. The stress controlling layer can include one or more attributes varies as a function of a lateral position based on a target variation of stresses in a semiconductor layer located directly under the stress controlling layer. Embodiments are further directed to a heterostructure including at least one stress controlling layer and a device including the heterostructure.

公开(公告)号：US20180188315A1

公开(公告)日：2018-07-05

申请号：US15857805

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Alexander Dobrinsky ,  Michael Shur

IPC: G01R31/26 ,  H01L33/00 ,  H01L33/06 ,  H01L33/12 ,  H01L33/14 ,  H01L33/32 ,  H01L33/40 ,  H01L33/46 ,  G01R31/00

Abstract: An optoelectronic device with at least one stress controlling structure and method of testing the device is disclosed. The optoelectronic device includes a stress controlling structure formed adjacent to a semiconductor heterostructure. The optoelectronic device can further include a stress inducing component that is configured to induce a change in stress within the stress controlling structure. The stress inducing component can induce a number of different stresses during a test of the optoelectronic device. A strain evaluator can evaluate the stresses within the semiconductor heterostructure as a function of a strain generated in the stress controlling structure.

公开(公告)号：US09997667B2

公开(公告)日：2018-06-12

申请号：US15495169

申请日：2017-04-24

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Remigijus Gaska ,  Jinwei Yang ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/14

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/15 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/207 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L33/325 ,  H01S5/2009 ,  H01S5/3211 ,  H01S5/3216 ,  H01S5/3407 ,  H01S5/34333

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

公开(公告)号：US09981051B2

公开(公告)日：2018-05-29

申请号：US14012637

申请日：2013-08-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim Shatalov ,  Timothy James Bettles ,  Yuri Bilenko ,  Saulius Smetona ,  Alexander Dobrinsky ,  Remigijus Gaska

IPC: F25D17/04 ,  A61L2/10

CPC classification number: A61L2/10 ,  F25D17/042 ,  F25D2317/0417

Abstract: Systems and methods for disinfecting a storage area and/or items within a storage area can include at least one ultraviolet radiation source configured to generate ultraviolet radiation directed within a storage area and a monitoring and control system. The monitoring and control system can be configured to monitor at least one of the storage area or a set of items located in the storage area and control ultraviolet radiation generated by the at least one ultraviolet radiation source based on the monitoring by delivering targeted ultraviolet radiation to at least one designated zone within the storage area.

公开(公告)号：US20180133351A1

公开(公告)日：2018-05-17

申请号：US15852988

申请日：2017-12-22

Applicant: Sensor Electronic Technology, Inc.

Inventor： Saulius Smetona ,  Alexander Dobrinsky ,  Yuri Bilenko ,  Michael Shur

IPC: A61L2/10 ,  H05B37/02 ,  H05B33/08

CPC classification number: A61L2/10 ,  A61L2202/14 ,  H05B33/0854 ,  H05B37/0227

Abstract: A solution for generating ultraviolet diffusive radiation is provided. A diffusive ultraviolet radiation illuminator includes at least one ultraviolet radiation source located within a reflective cavity that includes a plurality of surfaces. At least one of the plurality of surfaces can be configured to diffusively reflect at least 70% of the ultraviolet radiation and at least one of the plurality of surfaces can be configured to transmit at least 30% of the ultraviolet radiation and reflect at least 10% of the ultraviolet radiation.

公开(公告)号：US09966496B2

公开(公告)日：2018-05-08

申请号：US15096802

申请日：2016-04-12

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/02 ,  H01L33/12 ,  H01L33/14 ,  H01L33/30 ,  H01S5/02 ,  H01S5/323

CPC classification number: H01L33/0025 ,  H01L33/007 ,  H01L33/02 ,  H01L33/12 ,  H01L33/14 ,  H01L33/30 ,  H01L2933/0033 ,  H01S5/021 ,  H01S5/0213 ,  H01S5/32341 ,  H01S2301/173

Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.

公开(公告)号：US20180093002A1

公开(公告)日：2018-04-05

申请号：US15830274

申请日：2017-12-04

Applicant: Sensor Electronic Technology, Inc.

Inventor： Igor Agafonov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska ,  Saulius Smetona

IPC: A61L2/10 ,  A23L3/28

CPC classification number: A61L2/10 ,  A23L3/28

Abstract: A solution for disinfecting an area using ultraviolet radiation is provided. The solution can include an enclosure including at least one ultraviolet transparent window and a set of ultraviolet radiation sources located adjacent to the at least one ultraviolet transparent window. The set of ultraviolet radiation sources can be configured to generate ultraviolet radiation directed through the at least one ultraviolet transparent window. An input unit can be located on the enclosure and configured to generate an electrical signal in response to pressure applied to the enclosure. A control unit can be configured to manage the ultraviolet radiation by monitoring the electrical signal generated by the input unit and controlling, based on the monitoring, the ultraviolet radiation generated by the set of ultraviolet radiation sources.

公开(公告)号：US20180069154A1

公开(公告)日：2018-03-08

申请号：US15798909

申请日：2017-10-31

Applicant: Sensor Electronic Technology, Inc.

Inventor： Alexander Dobrinsky ,  Maxim S. Shatalov ,  Mikhail Gaevski ,  Michael Shur

IPC: H01L33/40 ,  H01L33/20 ,  H01L33/44 ,  H01L33/02 ,  H01L33/00

CPC classification number: H01L33/405 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03048 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/12 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/387 ,  H01L33/44 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0091

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. An n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second metallic contact layer can be located over a second portion of the n-type contact region, where the second metallic contact layer is formed of a reflective metallic material.

公开(公告)号：US09911895B2

公开(公告)日：2018-03-06

申请号：US15069178

申请日：2016-03-14

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Alexander Lunev ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/32 ,  H01L33/10 ,  H01L33/46 ,  H01S5/022

CPC classification number: H01L33/0025 ,  H01L33/0075 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.

公开(公告)号：US20180047870A1

公开(公告)日：2018-02-15

申请号：US15797263

申请日：2017-10-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L33/12 ,  H01L29/778 ,  H01L33/24 ,  H01L21/02 ,  H01L33/32 ,  H01L33/22 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/12 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.