公开(公告)号：US20160071844A1

公开(公告)日：2016-03-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8236

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract translation: 鳍状结构包括具有位于第一区域中的第一鳍状结构的基板和位于第二区域中的第二鳍状结构，其中第二鳍状结构包括梯形横截面轮廓部分 。 本发明还提供了形成该鳍状结构的两种方法。 在一种情况下，提供具有第一鳍状结构和第二鳍状结构的基板。 执行处理工艺以改变第二鳍状结构的顶部的外表面，从而形成修改部分。 进行去除处理以通过对第一鳍状结构和第二鳍状结构以及改性部分的高去除选择性去除改性部分，由此第二鳍状结构具有梯形横截面 形成轮廓部分。

公开(公告)号：US20160064521A1

公开(公告)日：2016-03-03

申请号：US14935441

申请日：2015-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/225 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US20160049496A1

公开(公告)日：2016-02-18

申请号：US14495907

申请日：2014-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

Abstract translation: 提供了包括栅极结构，外延隔离物和外延结构的MOS晶体管。 栅极结构设置在基板上。 除了栅极结构之外，外延衬垫设置在衬底上，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 外延结构除了外延间隔物之外还设置在基板中。 半导体工艺包括用于形成外延结构的以下步骤。 在基板上形成栅极结构。 除了用于限定外延结构的位置的栅极结构之外，在衬底上形成外延衬垫，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 该外延结构除了外延间隔物外还形成在基板中。

公开(公告)号：US09214395B2

公开(公告)日：2015-12-15

申请号：US13802542

申请日：2013-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US09006058B1

公开(公告)日：2015-04-14

申请号：US14150489

申请日：2014-01-08

Applicant: United Microelectronics Corp.

Inventor： Tung-Ming Chen ,  Yu-Chun Huang ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  I-Fang Huang

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is described. A semiconductor substrate is provided, wherein the substrate has a first area and a second area. A first gate structure and a second gate structure are formed over the substrate in the first area and the substrate in the second area, respectively. A first spacer is framed on the sidewall of each gate structure. At least one etching process including at least one wet etching process is performed. The first spacer is removed. A second spacer is formed on the sidewall of each gate structure. A mask layer is formed in the second area. Ion implantation is formed using the mask layer, the first gate structure and the second spacer as a mask to form S/D extensions in the substrate beside the first gate structure in the first area. The mask layer is then removed.

Abstract translation: 对半导体装置的制造方法进行说明。 提供一种半导体衬底，其中衬底具有第一区域和第二区域。 第一栅极结构和第二栅极结构分别在第一区域和第二区域中的衬底上形成在衬底上。 第一间隔件框架在每个栅极结构的侧壁上。 执行包括至少一个湿蚀刻工艺的至少一个蚀刻工艺。 第一个垫片被去除。 在每个栅极结构的侧壁上形成第二间隔物。 在第二区域中形成掩模层。 使用掩模层，第一栅极结构和第二间隔物作为掩模形成离子注入，以在第一区域中的第一栅极结构旁边的衬底中形成S / D延伸。 然后去除掩模层。

公开(公告)号：US08753902B1

公开(公告)日：2014-06-17

申请号：US13802494

申请日：2013-03-13

Applicant: United Microelectronics Corp.

Inventor： Chia-Jong Liu ,  Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: G01R31/26

CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/3086 ,  H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.

Abstract translation: 控制用于形成外延结构的蚀刻工艺的方法包括以下步骤。 提供了具有栅极的基板。 在栅极旁边的衬底上形成间隔物以限定外延结构的位置。 测量间隔物的厚度。 第一蚀刻工艺的蚀刻时间根据厚度设定。 执行第一蚀刻工艺以在间隔物旁边的衬底中形成凹部。 在凹部中形成外延结构。