公开(公告)号：US09331171B2

公开(公告)日：2016-05-03

申请号：US14831881

申请日：2015-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/665 ,  H01L21/76814 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/785

Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.

Abstract translation: 本发明提供一种半导体结构的制造方法，包括以下步骤。 首先，提供基板，在基板上形成第一介电层，金属栅极设置在第一介电层中，并且至少一个源极/漏极区（S / D区）设置在金属栅极的两侧 然后在第一介电层上形成第二电介质层，然后执行第一蚀刻工艺以在第一电介质层和第二电介质层中形成多个第一沟槽，其中第一沟槽暴露每个S / D区域。 然后，进行自对准处理以在每个第一沟槽中形成自对准硅化物层，然后执行第二蚀刻工艺以在第一介电层和第二介电层中形成多个第二沟槽，并且第二沟槽暴露金属栅极 。

公开(公告)号：US20160104647A1

公开(公告)日：2016-04-14

申请号：US14539225

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

公开(公告)号：US20160104637A1

公开(公告)日：2016-04-14

申请号：US14510100

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

Abstract translation: 制造接触结构的方法包括以下步骤：在其上提供具有半导体器件和层间电介质的衬底，其中半导体器件包括栅极结构和源极/漏极区; 在基板上形成具有条纹孔的图案化掩模层，并且在基板上同时形成条形掩模层; 在所述基板上形成具有多个槽孔的图案化光致抗蚀剂层，其中所述槽孔中的至少一个设置在所述源极/漏极区域正上方; 并且通过使用图案化掩模层，条形掩模层和图案化光致抗蚀剂层作为蚀刻掩模在层间电介质中形成接触孔，并且当步骤 形成接触孔。

公开(公告)号：US09196352B2

公开(公告)日：2015-11-24

申请号：US13776589

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Po-Chao Tsao ,  Shu-Ru Wang ,  Chia-Wei Huang ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang

IPC: H01L21/70 ,  G11C11/00 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract translation: 公开了一种静态随机存取存储器单元布局结构，其中，槽触点设置在一个有源区上，另一个位于一个有源区上。 还公开了一种静态随机存取存储单元单元结构及其制造方法，其中，在上拉晶体管和下拉晶体管的漏极上设置一个槽触点，并且设置金属零互连 在槽触点和另一个上拉晶体管的栅极线上。 因此，没有垂直和水平的金属零互连，没有两次蚀刻的地方。 可以避免缝合凹陷引起的泄漏接头。

公开(公告)号：US20150270261A1

公开(公告)日：2015-09-24

申请号：US14730230

申请日：2015-06-03

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L27/06 ,  H01L21/768 ,  H01L29/40 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09064814B2

公开(公告)日：2015-06-23

申请号：US13921221

申请日：2013-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ching Wu ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L27/092 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238

CPC classification number: H01L21/311 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.

Abstract translation: 半导体器件的制造方法首先提供至少形成有第一晶体管的衬底。 第一晶体管包括第一导电类型。 第一晶体管还包括第一金属栅极和覆盖第一金属栅极的侧壁的保护层。 去除第一金属栅极的一部分以形成第一凹槽，然后除去保护层的一部分以形成第二凹槽。 然后，在第二凹部中形成蚀刻停止层。

公开(公告)号：US20150011090A1

公开(公告)日：2015-01-08

申请号：US13934236

申请日：2013-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao ,  Jun-Jie Wang ,  Chih-Sen Huang

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/3086 ,  H01L29/66795

Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.

Abstract translation: 鳍状结构形成工序包括以下工序。 第一心轴和第二心轴形成在基底上。 形成第一间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻暴露的第一间隔物材料以在第一心轴旁边的基底上形成第一间隔物。 形成第二间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻第二间隔物材料和第一间隔物材料，以在第二心轴旁边的基底上形成第二间隔物，以及在第一心轴旁边的包括在基底上的第一间隔物的第三间隔物。 第二间隔物和第三间隔物的布局被转移到基底，因此分别形成具有不同宽度的第二鳍状结构和第一鳍状结构。

公开(公告)号：US08785283B2

公开(公告)日：2014-07-22

申请号：US13705183

申请日：2012-12-05

Applicant: United Microelectronics Corp.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/66

CPC classification number: H01L21/76816 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract translation: 本发明提供一种形成具有金属连接的半导体结构的方法。 提供衬底，并在其上形成晶体管和第一ILD层。 第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。 在第一ILD层上形成第二ILD层和第三ILD层。 形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。 接下来，加深第一开口和第二开口。 最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

公开(公告)号：US08765546B1

公开(公告)日：2014-07-01

申请号：US13925812

申请日：2013-06-24

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang

IPC: H01L27/088

CPC classification number: H01L21/823431

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.

Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板上形成翅片状结构; 在所述鳍状结构上形成第一栅极结构; 在与所述第一栅极结构相邻的所述鳍状结构中形成第一外延层; 在所述第一栅极结构和所述第一外延层上形成层间电介质层; 在所述层间电介质层中形成开口以暴露所述第一外延层; 在所述第一外延层上形成硅帽; 并在开口中形成接触塞。

公开(公告)号：US20140151763A1

公开(公告)日：2014-06-05

申请号：US13705175

申请日：2012-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L23/532 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供了一种半导体结构，其包括衬底，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上。 第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。 第二ILD层设置在第一ILD层上。 第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。 第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。 本发明还提供了制备该方法的方法。