公开(公告)号：US20180342425A1

公开(公告)日：2018-11-29

申请号：US16038196

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.

公开(公告)号：US10103019B1

公开(公告)日：2018-10-16

申请号：US15725258

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/20 ,  H01L21/02 ,  G02B1/11 ,  H01L51/00

Abstract: The present invention provides a method of fabricating a semiconductor structure. Firstly, a substrate is provided, a dense region and an isolation region are defined, next, a first dielectric layer is formed on the dense region and the isolation region, and then a plurality of first recesses are formed in the first dielectric layer within the dense region, and a second recess is formed in the first dielectric layer within the isolation region, wherein the width of the second recess is greater than three times of the width of each first recess. Afterwards, a second dielectric layer is then filled in each first recess and the second recess, wherein a top surface of the second dielectric layer within the isolation region is higher than a top surface of the second dielectric layer within the dense region. Next, an etching back process is performed, to remove the second dielectric layer.

公开(公告)号：US20180226410A1

公开(公告)日：2018-08-09

申请号：US15884415

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

公开(公告)号：US20180190659A1

公开(公告)日：2018-07-05

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10855 ,  H01L21/02071 ,  H01L21/28247 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US09793382B2

公开(公告)日：2017-10-17

申请号：US15470905

申请日：2017-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

公开(公告)号：US09673100B2

公开(公告)日：2017-06-06

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L27/088 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

公开(公告)号：US20170084722A1

公开(公告)日：2017-03-23

申请号：US14919716

申请日：2015-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US20160225662A1

公开(公告)日：2016-08-04

申请号：US14612235

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在ILD层和栅极结构上形成介电层; 在介电层和ILD层中形成开口; 在介质层和开口中形成有机介电层（ODL）; 去除部分ODL; 去除用于延伸开口的电介质层的一部分; 去除剩余的ODL; 并在开口中形成接触塞。

公开(公告)号：US09196352B2

公开(公告)日：2015-11-24

申请号：US13776589

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Po-Chao Tsao ,  Shu-Ru Wang ,  Chia-Wei Huang ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang

IPC: H01L21/70 ,  G11C11/00 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract translation: 公开了一种静态随机存取存储器单元布局结构，其中，槽触点设置在一个有源区上，另一个位于一个有源区上。 还公开了一种静态随机存取存储单元单元结构及其制造方法，其中，在上拉晶体管和下拉晶体管的漏极上设置一个槽触点，并且设置金属零互连 在槽触点和另一个上拉晶体管的栅极线上。 因此，没有垂直和水平的金属零互连，没有两次蚀刻的地方。 可以避免缝合凹陷引起的泄漏接头。

公开(公告)号：US20150214068A1

公开(公告)日：2015-07-30

申请号：US14162755

申请日：2014-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

IPC: H01L21/311 ,  H01L21/027

CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/76816

Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.

Abstract translation: 提供了一种执行蚀刻工艺的方法。 提供了一种衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 在基板上形成包括有机层，底部防反射涂层（BARC）和光致抗蚀剂层的三层结构。 去除第二区域中的光致抗蚀剂层和BARC。 通过使用BARC和/或光致抗蚀剂层作为掩模，进行蚀刻工艺以去除第二区域中的有机层，其中蚀刻工艺使用蚀刻剂包括CO 2。