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公开(公告)号：JP2008136127A
公开(公告)日：2008-06-12
申请号：JP2006322211
申请日：2006-11-29
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor： YASUI SHOJI , TSUCHIYA HIROTOSHI , SHIMIZU YOSHIKO , TODA AKIHIKO , MAEJIMA TOSHIO
Abstract: PROBLEM TO BE SOLVED: To suppress offset even when the relevant offset occurs in the signal level of an input signal. SOLUTION: An offset cancel apparatus S1 is configured to complementarily change a resistance value between the inverted input terminal and the signal input terminal IN of an operational amplifier 20A for differential amplification circuit and a resistance value between the inverted input terminal and an output terminal, to gradually reduce the potential of an output signal Vout and to specify each resistance value in such a way that the potential becomes "0" finally, and carries out offset cancel using the resistance values. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：即使当在输入信号的信号电平中出现相关偏移时也抑制偏移。 解决方案：偏移消除装置S1被配置为互补地改变用于差分放大电路的运算放大器20A的反相输入端和信号输入端IN之间的电阻值，以及反相输入端和输出端之间的电阻值 端子，逐渐降低输出信号Vout的电位，并最终以电位变为“0”的方式指定每个电阻值，并使用电阻值进行偏移消除。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2006042296A
公开(公告)日：2006-02-09
申请号：JP2004297579
申请日：2004-10-12
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor： MAEJIMA TOSHIO
CPC classification number: H03F3/217 , H03F1/34 , H03F3/2173 , H03F2200/78
Abstract: PROBLEM TO BE SOLVED: To provide a class-D amplifier in which a DC voltage component in an output can be reduced to nearly zero volt without using a transformer, and distortion and a power loss can be reduced. SOLUTION: A class-D amplifier includes, an operational amplifier 11 and capacitors C1, C2 which constitute an integrator for integrating a difference between a plus-side input signal and a minus-side input signal which constitute analog input signals; delay circuits 21, 22 for delaying a phase of a triangular wave by a desirable very small angle; resistors R5, R6, R7, R8, R9, R10, R11, R12 which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits 21, 22 with each other; comparators 12, 13 for comparing outputs of the synthesizing circuit with each other; AND circuits 31, 32 which constitute a buffer for inputting outputs of the comparators 12, 13; and resistors R3, R4 for feeding back an output of the buffer to an input side of the integrator. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种D类放大器，其中输出中的直流电压分量可以在不使用变压器的情况下降低到几乎零伏特，并且可以减小失真和功率损耗。 解决方案：D类放大器包括：运算放大器11和电容器C1，C2，其构成用于积分构成模拟输入信号的正侧输入信号和负侧输入信号之间的差的积分器; 延迟电路21,22，用于将三角波的相位延迟期望的非常小的角度; 电阻器R5，R6，R7，R8，R9，R10，R11，R12，它们构成用于合成积分器的输出，三角波和延迟电路21,22的输出的合成电路; 比较器12,13，用于比较合成电路的输出; AND电路31,32构成用于输入比较器12,13的输出的缓冲器; 以及用于将缓冲器的输出反馈到积分器的输入侧的电阻器R3，R4。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2005123949A
公开(公告)日：2005-05-12
申请号：JP2003357631
申请日：2003-10-17
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor： MAEJIMA TOSHIO
IPC: H03F3/217
CPC classification number: H03F3/2171
Abstract: PROBLEM TO BE SOLVED: To provide a class D amplifier suppressing output peak at the time of no load or at the time of light load of the class D amplifier.
SOLUTION: The class D amplifier outputs an analog input signal by performing pulse width modulation to it and is characterized by having a differentiation circuit 15 which differentiates output of the class D amplifier and a negative feedback circuit which performs negative feedback of the output of the differentiation circuit 15 to an input side of the class D amplifier.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供抑制D类放大器的无负载时或者轻负载时的输出峰值的D类放大器。 解决方案：D类放大器通过对其进行脉冲宽度调制输出模拟输入信号，其特征在于具有微分电路15，其区分D类放大器的输出和执行负输出的负反馈电路 差分电路15的输入端到D类放大器的输入侧。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2004214933A
公开(公告)日：2004-07-29
申请号：JP2002381861
申请日：2002-12-27
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor： MAEJIMA TOSHIO
Abstract: PROBLEM TO BE SOLVED: To provide a pulse width modulation amplifier capable of protecting a speaker from a DC current flowing through the speaker when one signal input terminal of the speaker is connected to one output terminal of a BTL output circuit and another signal input terminal of the speaker is connected to ground.
SOLUTION: When a voltage Vsence across a resistor R46 exceeds a reference negative voltage, a comparator CMP 32 outputs a high level signal. The output of the comparator CMP 32 is applied to a stop input of a driver 13 as a decision output. When the comparator CMP 32 outputs the high level signal to the stop input of the driver 13, the driver 13 stops switching operations to field effect transistors PNM1, PPM1, PNM2, PPM2.
COPYRIGHT: (C)2004,JPO&NCIPI-
公开(公告)号：JP2001160722A
公开(公告)日：2001-06-12
申请号：JP34394799
申请日：1999-12-02
Applicant: YAMAHA CORP
Inventor： MAEJIMA TOSHIO
Abstract: PROBLEM TO BE SOLVED: To provide a differential amplifier circuit for stabilizing the operating point of an output circuit even when manufacture dispersion or power supply fluctuation or the like is present and extremely reducing a bias current at the time of non-signal compared to a maximum output current. SOLUTION: This differential amplifier circuit is provided with an input circuit 10 for generating the differential voltage signals of + side input signals and - side input signals, a feedback bias circuit 20 for inputting the differential voltage signals supplied from the input circuit 10, supplying a bias voltage equivalent to the differential voltage signals, feeding back an output current and feedback-controlling the bias voltage, the output circuit 30 for supplying the output current corresponding to the bias voltage to a load side and a current detection circuit 40 for detecting the output current and supplying it to the feedback bias circuit 20. The differential amplifier circuit defines the current value of the bias voltage as a value close to zero when the differential voltage signal is the non-signal and performs AB class amplification.
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Patent Agency Ranking
公开(公告)号：JP2001156640A
公开(公告)日：2001-06-08
申请号：JP34148299
申请日：1999-11-30
Applicant: YAMAHA CORP
Inventor： TODA AKIHIKO , MAEJIMA TOSHIO , NORO MASAO
Abstract: PROBLEM TO BE SOLVED: To provide a resistor string digital/analog converter that can increase the bits of converted data without increasing number of resistors. SOLUTION: High-order four bits of data to be converter are applied to a decoder 1 and low-order four bits are applied to a decoder 3 via an inversion circuit 2. The decoder 1 decodes the high-order four bits and makes one of FET F0-F15 conductive based on the decoding result. Thus, one of voltages at connecting points of resistors r0-r15 connected in series is selected and applied to an operational amplifier 6. Similarly a voltage corresponding to the low-order four bits of the data to be converted is applied to an operational amplifier 7. Then an output of the operational amplifier 7 is divided into 1/16 by resistors ra, rb, this voltage is added to a voltage applied to the operational amplifier 6 to obtain an analog voltage after conversion.
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公开(公告)号：JPH11260093A
公开(公告)日：1999-09-24
申请号：JP5972798
申请日：1998-03-11
Applicant: YAMAHA CORP
Inventor： TODA AKIHIKO , NORO MASAO , MAEJIMA TOSHIO
Abstract: PROBLEM TO BE SOLVED: To provide a delay circuit in which low frequency noise disturbance can be removed. SOLUTION: At the time of writing, an input analog signal Vin is stored in odd number memory cell M1, M3,..., Mn-1 and an inverted input analog signal Vin is stored in even number memory cell M2, M4,..., Mn. At the time of reading, a signal read out from even number memory cell M2, M4,..., Mn is inverted and combined, by a switch SH0, with a signal read out from odd number memory cell M1, M3, ..., Mn-1 to produce an output analog signal Vout. When a low frequency noise is mixed in the delay circuit, a voltage value stored in a capacitor C1-Cn is varied but since it is read out while repeating forward and reverse rotation, noise component can be shifted to a separable high region frequency.
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公开(公告)号：JPH0945867A
公开(公告)日：1997-02-14
申请号：JP21680195
申请日：1995-08-02
Applicant: YAMAHA CORP
Inventor： TAKAHASHI TOSHIYUKI , MAKINO TOUHACHI , MAEJIMA TOSHIO
IPC: H01L23/12 , H01L21/265 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/78
Abstract: PROBLEM TO BE SOLVED: To enable MOS transistors of different threshold values to be easily integrated into a semiconductor device by a method wherein ion implantation conditions are set conforming to both a polysilicon gate structure and a polycide gate structure. SOLUTION: A gate oxide film 3 is formed on a silicon substrate 1. A gate electrode G1 is formed in a region of a D-type MOS transistor Q1 on the gate oxide film 3 by patterning a first polysilicon film 4, and a polycide gate electrode G2 of laminated structure composed of the first polysilicon film 4 and a silicide film 8 is formed in a region of an E-type MOS transistor Q2 by patterning. An ion implantation process is carried out using the gates G1 and G2 as a mask for forming an LDD structure. At this point, the conditions for ion implantation are so selected as to enable ions to penetrate through the polysilicon gate electrode G1 on a D-type MOS transistor Q1 side but not to penetrate through the polycide gate electrode G2 on an E-type MOS transistor Q2 to form ion implanted layers.
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公开(公告)号：JPH08265074A
公开(公告)日：1996-10-11
申请号：JP9308295
申请日：1995-03-27
Applicant: YAMAHA CORP
Inventor： MAEJIMA TOSHIO
Abstract: PURPOSE: To eliminate the need for an amplifier circuit for output level adjustment by decreasing a fluctuation in an output signal level due to dispersion in elements or temperature dependency. CONSTITUTION: The control circuit has a voltage amplifier circuit 11 using an operational amplifier OP and an input signal attenuation circuit 12 attenuating selectively an input signal level to the amplifier circuit 11 and a current mirror differential amplifier circuit 13 receiving a lower reference voltage Vref than a DC bias VCOM and a time constant circuit 14 as an output level detection circuit detecting an output signal level of the voltage amplifier circuit 11 to apply feedback control to the input signal attenuation circuit 12. The input signal attenuation circuit 12 is made up of an input resistor R1 and a PMOS transistor(TR) M1 whose source connects to a DC bias VCOM terminal. The ON-resistance of the PMOS TR M1 is controlled by the time constant circuit 14 controlled by the output of the differential amplifier circuit 13.
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公开(公告)号：JPH047913A
公开(公告)日：1992-01-13
申请号：JP10991590
申请日：1990-04-25
Applicant: YAMAHA CORP
Inventor： ISHIDA KATSUHIKO , MAEJIMA TOSHIO , OGITA MINORU
Abstract: PURPOSE:To eliminate zero cross distortion with simple constitution and to expand the dynamic range by applying DA conversion in a form of zero point shift based on a digital bias data. CONSTITUTION:An LSB-MSB data SD is inputted to a register 10 and converted into a parallel data PD. The data PD is fed to an adder 12, in which the data is added with a bias data BD from a generator 14. The added data SFD is fed to a selector 16 as an input A and the data PD is fed as an input B and the data selection is controlled in response to a selection control input. A compa rator 18 compares the data PD with a reference data D40. A comparison output CO is fed to the selector 16 as a selection control input. A current output DAC20 DA-converts an output data SO from the selector 16. The switching operation of a changeover circuit 22 is controlled in response to the output CO and an analog signal corresponding to the input is obtained.
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