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    PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    43.
    发明申请
    PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 有权

    公开(公告)号：US20210303504A1

    公开(公告)日：2021-09-30

    申请号：US17199418

    申请日：2021-03-11

    Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

    Inventor： Rolf Nandlinger ,  Radek Olexa

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F9/30

    Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

    DEVICE AND METHOD FOR CHECKING FRAMES FROM A COMMUNICATION BUS
    44.
    发明申请
    DEVICE AND METHOD FOR CHECKING FRAMES FROM A COMMUNICATION BUS 有权

    公开(公告)号：US20210281497A1

    公开(公告)日：2021-09-09

    申请号：US17182914

    申请日：2021-02-23

    Applicant: STMicroelectronics Application GMBH

    Inventor： Fred Rennig

    IPC: H04L12/26

    Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

    Hardware secure module, related processing system, integrated circuit, device and method
    45.
    发明授权
    Hardware secure module, related processing system, integrated circuit, device and method 有权

    公开(公告)号：US11032067B2

    公开(公告)日：2021-06-08

    申请号：US16022110

    申请日：2018-06-28

    Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

    Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

    IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

    Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

    Processing system, related integrated circuit and method
    46.
    发明授权
    Processing system, related integrated circuit and method 有权

    公开(公告)号：US10949570B2

    公开(公告)日：2021-03-16

    申请号：US16039103

    申请日：2018-07-18

    Applicant: STMicroelectronics Application GmbH

    Inventor： Roberto Colombo

    IPC: G06F21/71 ,  G06F21/44 ,  G06F21/62 ,  G06F21/79

    Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.

    Configurable cryptographic processor with integrated DMA interface for secure data handling
    47.
    发明授权
    Configurable cryptographic processor with integrated DMA interface for secure data handling 有权

    公开(公告)号：US12117949B2

    公开(公告)日：2024-10-15

    申请号：US18364786

    申请日：2023-08-03

    Applicant: STMicroelectronics Application GMBH

    Inventor： Rolf Nandlinger ,  Roberto Colombo

    IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

    CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

    Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

    Processing system, related integrated circuit, device and method
    50.
    发明授权
    Processing system, related integrated circuit, device and method 有权

    公开(公告)号：US11915008B2

    公开(公告)日：2024-02-27

    申请号：US17654537

    申请日：2022-03-11

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

    Inventor： Roberto Colombo ,  Nicolas Bernard Rene Grossier ,  Fabio Enrico Carlo Disegni

    IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/30

    CPC classification number: G06F9/4403 ,  G06F9/30101

    Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

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