公开(公告)号：US20170040255A1

公开(公告)日：2017-02-09

申请号：US15038623

申请日：2013-12-23

Applicant: Uwe ZILLMANN ,  Andre SCHAEFER ,  Ruchir SARASWAT ,  Guido DROEGE ,  Rinkle JAIN ,  Nicholas P. COWLEY ,  INTEL CORPORATION

Inventor： KEVIN J. LEE ,  RUCHIR SARASWAT ,  UWE ZILLMANN ,  NICHOLAS P. COWLEY ,  ANDRE SCHAEFER ,  RINKLE JAIN ,  GUIDO DROEGE

IPC: H01L23/522 ,  H01L21/822 ,  H01L23/492 ,  H01L21/48 ,  H01L27/06 ,  H01L23/498

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0657 ,  H01L27/0629 ,  H01L28/90 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract translation: 公开了用于在半导体管芯中形成通孔通孔（TBV）隔离同轴电容器的技术。 在一些实施例中，使用所公开的技术提供的圆柱形电容器可以包括例如由介电材料和外导体板包围的导电TBV。 根据一些实施例，TBV和外板可以形成为例如以同轴布置彼此自对准。 所公开的电容器可以延伸穿过主模具的主体，使得其端子在其上表面和/或下表面上可接近。 因此，根据一些实施例，在一些情况下，主体管芯可以与另一个管芯电连接以提供管芯堆叠或其他三维集成电路（3D IC）。 在一些情况下，所公开的电容器可用于例如在开关电容器电压调节器（SCVR）中提供集成电容。

公开(公告)号：US09026767B2

公开(公告)日：2015-05-05

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/10 ,  G06F12/06

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US20140281193A1

公开(公告)日：2014-09-18

申请号：US13835864

申请日：2013-03-15

Applicant: ANDRE SCHAEFER

Inventor： ANDRE SCHAEFER

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/10 ,  G11C7/109 ,  G11C11/4076

Abstract: A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.

Abstract translation: 紧密接近存储器布置保持DQ或数据线之间的点对点关联，DRAM模块在存储器控制器-DRAM接口的DRAM侧采用无时钟状态机，使得存储器控制器侧的单个FIFO同步或命令 DRAM提取结果。 添加行地址（ROW-ADD）和列地址（COL-ADD）选通可以减少延迟和功耗。 接近点到点DRAM接口使得DRAM侧FIFO在诸如直接堆叠的3D DRAM之类的接口中冗余，这些存储器位于托管存储器控制器的逻辑管芯之上。 紧密的点对点布置消除了DRAM内部FIFO和延迟方案，导致内存控制器内部时钟域跨越FIFO。

公开(公告)号：US20140092574A1

公开(公告)日：2014-04-03

申请号：US13631092

申请日：2012-09-28

Applicant: Uwe ZILLMANN ,  Andre SCHAEFER ,  Ruchir SARASWAT ,  Telesphor KAMGAING ,  Paul B. FISCHER ,  Guido DROEGE

Inventor： Uwe ZILLMANN ,  Andre SCHAEFER ,  Ruchir SARASWAT ,  Telesphor KAMGAING ,  Paul B. FISCHER ,  Guido DROEGE

IPC: H05K7/02 ,  H05K3/30

CPC classification number: G06F1/3296 ,  H01L2924/0002 ,  H05K1/0262 ,  H05K1/165 ,  Y02D10/172 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry.

Abstract translation: 在芯片级与微电子器件集成的磁性增强型电感器。 在实施例中，磁增强电感器包括具有填充金属的穿通衬底通孔（TSV），以承载靠近设置在TSV通过的衬底上的磁性层的电流。 在某些磁增强电感器实施例中，TSV填充金属设置在衬在TSV内的磁性材料内。 在某些磁增强电感器实施例中，磁增强电感器包括靠近基板一侧的磁性材料层设置的多个互连TSV。 在实施例中，设置在衬底的第一侧上的电压调节电路与利用穿过衬底的TSV的一个或多个磁增强电感器集成。 在另外的实施例中，在与磁增强电感器相同的衬底上或在其上堆叠的另一衬底上的集成电路完成VR和/或由VR电路供电。

公开(公告)号：US20140003758A1

公开(公告)日：2014-01-02

申请号：US13985095

申请日：2011-11-15

Applicant: Marc-Andre Schaefer

Inventor： Marc-Andre Schaefer

IPC: F16C33/46

CPC classification number: F16C33/46 ,  F16C33/4605 ,  F16C41/04 ,  F16C43/04 ,  F16C2326/02

Abstract: A roller bearing cage 16 with roller bearing pockets 18 which are arranged one next to the other in the circumferential direction and have the purpose of holding load-bearing roller bodies 10 of a roller bearing, wherein at least one end piece 14 which engages behind a roller bearing component 12 is formed on the roller bearing cage 16. The end piece 14, which is ideally embodied as a retaining claw, holds the inner ring and the roller body 10 together, but can be removed after or during the assembly by means of a predetermined rupture point 15, in order to make room for a further component, such as for example a sealing arrangement. As a result, despite the installation assistance, optimum use of the installation space is provided.

Abstract translation: 一种滚子轴承保持架16，其具有在圆周方向上彼此相邻布置的滚子轴承座18，并且具有保持滚子轴承的承载滚子体10的目的，其中至少一个端部件14 滚子轴承部件12形成在滚子轴承保持器16上。理想地实施为保持爪的端部件14将内圈和滚子主体10保持在一起，但是可以在组装之后或组装期间通过 预定的破裂点15，以便为另外的部件（例如密封装置）腾出空间。 因此，尽管有安装帮助，但是提供了最佳使用安装空间。

公开(公告)号：US20110044569A1

公开(公告)日：2011-02-24

申请号：US12810603

申请日：2008-11-12

Applicant: Alexander Haepp ,  Robert Heuber ,  Marc-Andre Schaefer ,  Wilhelm Walter

Inventor： Alexander Haepp ,  Robert Heuber ,  Marc-Andre Schaefer ,  Wilhelm Walter

IPC: F16C33/80 ,  F16J15/16

CPC classification number: F16C33/7883 ,  F16C19/364 ,  F16C19/543 ,  F16C33/586 ,  F16C33/768 ,  F16C33/7813 ,  F16C33/805 ,  F16C2326/02 ,  F16J15/3256 ,  F16J15/3264

Abstract: A compact cassette seal and a corresponding wheel hearing for a passenger car or truck. The cassette seal has a bent sheet-metal ring which is and/or can be non-rotatably connected to a radially inner component and an annular sealing system which is non-rotatably connected to a radially outer component. The sealing system has a bearing ring and a radially peripheral seal with at least one sealing lip. The seal is secured to the bearing ring and the sealing lips resting on the bent sheet-metal ring in a sealing manner. A radially outer ring end section of the sealing system defines a labyrinth seal with a bent sheet-metal section of the bent sheet-metal ring. The bent sheet-metal section radially overlaps the ring end section on the exterior thereby forming an axially aligned or substantially axially aligned labyrinth seal section of the labyrinth seal.

Abstract translation: 一个小型的盒式密封件和一个乘用车或卡车的相应的车轮听力。 盒式密封件具有弯曲的金属板环，该环形密封环与径向内部部件和不可旋转地连接到径向外部部件的环形密封系统是不可旋转的连接的。 密封系统具有轴承环和具有至少一个密封唇的径向周向密封。 密封件以密封方式固定到轴承环上并且密封唇靠在弯曲的金属板上。 密封系统的径向外环端部限定了弯曲的金属片弯曲的金属片弯曲的迷宫式密封件。 弯曲的金属片部分径向地与外部的环形端部重叠，从而形成迷宫式密封件的轴向对准或基本轴向对准的迷宫式密封部分。

公开(公告)号：US20070091711A1

公开(公告)日：2007-04-26

申请号：US11259376

申请日：2005-10-26

Applicant: Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

Inventor： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

Abstract translation: 用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。 数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。 附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

公开(公告)号：US07049930B2

公开(公告)日：2006-05-23

申请号：US10663354

申请日：2003-09-16

Applicant: Joachim Schnabel ,  Andre Schaefer ,  Xaver Obergrussberger ,  Sebastian Mosler

Inventor： Joachim Schnabel ,  Andre Schaefer ,  Xaver Obergrussberger ,  Sebastian Mosler

IPC: H01C1/01

CPC classification number: H01L27/105 ,  H01L27/0207 ,  H01L27/0802 ,  H01L27/10897 ,  H01L27/118

Abstract: An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.

Abstract translation: 共同位于半导体器件的同一个阱中的多个电阻器的布置以及包括至少一个这样的电阻器布置的半导体器件，其中当沿电阻器的纵向方向观察时，电阻器被移位 相互之间。

公开(公告)号：US06917562B2

公开(公告)日：2005-07-12

申请号：US10658741

申请日：2003-09-10

Applicant: Andre Schaefer ,  Johann Pfeiffer ,  Kazimierz Szczypinski

Inventor： Andre Schaefer ,  Johann Pfeiffer ,  Kazimierz Szczypinski

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/00

CPC classification number: G11C29/12015 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)—, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).

Abstract translation: 本发明涉及具有连接（3b）的组件以及至少一个另外的连接（3a），由此差分输入时钟脉冲（CLK，CLK，T CLK，/ CLK， 可以应用于连接（3a，3b）或施加到连接（3b）上的单个输入时钟脉冲（CLK，CLK＆lt; T＆gt;）和 或另外的连接（3a） - ，并且其中所述组件另外具有第一和第二脉冲中继设备（50,51），其中所述第一脉冲中继设备（50）已被提供用于中继差分输入时钟 用于中继单个输入时钟脉冲（CLK，CLK T ）。

公开(公告)号：US06911732B2

公开(公告)日：2005-06-28

申请号：US10137511

申请日：2002-04-30

Applicant: Simon Muff ,  Martin Gall ,  Andre Schaefer ,  Georg Braun

Inventor： Simon Muff ,  Martin Gall ,  Andre Schaefer ,  Georg Braun

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66

CPC classification number: H01L23/66 ,  H01L2224/49175 ,  H01L2924/15173 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

Abstract translation: 一种集成在壳体中的集成电路，其具有装配到壳体的连接销，用于将外壳连接到外部电路的信号线，每个连接引脚通过相关布线连接到集成在外壳中的电路的接触焊盘， 在外部电路和集成电路之间交换信号，其中最小化相关布线的线路长度，要连接到用于高频信号的信号线的连接引脚被集中地安装到壳体。