公开(公告)号：US20130246734A1

公开(公告)日：2013-09-19

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US09026767B2

公开(公告)日：2015-05-05

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/10 ,  G06F12/06

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US08135936B2

公开(公告)日：2012-03-13

申请号：US12646248

申请日：2009-12-23

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0607 ,  Y02D10/13

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US20110153908A1

公开(公告)日：2011-06-23

申请号：US12646248

申请日：2009-12-23

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0607 ,  Y02D10/13

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US09311983B2

公开(公告)日：2016-04-12

申请号：US14320249

申请日：2014-06-30

Applicant: Andre Schaefer

Inventor： Andre Schaefer

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.

Abstract translation: 刷新电压控制引擎选择性地施加不同的高电压以用于刷新操作。 控制引擎可以检测存储器件的一部分需要刷新，并且确定刷新周期时间对于存储器件的该部分的状态来说太短。 存储器件通常具有基于设备和系统架构的刷新之间的相关联的刷新周期时间或时间。 控制引擎可以产生一个或多个控制信号，以使系统施加过充电刷新，以使刷新操作对存储器件的一部分进行过充电，以延长存储器件部分的刷新周期时间。

公开(公告)号：US08037375B2

公开(公告)日：2011-10-11

申请号：US12459420

申请日：2009-06-30

Applicant: Andre Schaefer

Inventor： Andre Schaefer

IPC: G06F11/00

CPC classification number: G06F13/1689 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C29/02 ,  G11C29/023 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract translation: 公开了一种方法，装置和系统。 在一个实施例中，方法包括确定存储器的有效数据眼睛的左边缘和右边缘。 该方法通过在存储器的操作期间周期性地检查左右边缘以进行移动来继续。 如果检测到移动，则该方法使用更新的左边缘和右边缘重新训练有效的数据眼睛。

公开(公告)号：US20070061494A1

公开(公告)日：2007-03-15

申请号：US11214068

申请日：2005-08-30

Applicant: Paul Wallner ,  Andre Schaefer ,  Thomas Hein

Inventor： Paul Wallner ,  Andre Schaefer ,  Thomas Hein

IPC: G06F5/00

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/1084

Abstract: In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames in accordance with a predefined protocol. The semiconductor memory system and predefined protocol are adapted to transfer write data mask bits in a close relation to respectively associated write data units within one write data/command stream. An interface section between a reception interface and a memory core of the semiconductor memory chip includes a frame decoder and a intermediate data buffer.

Abstract translation: 在半导体存储器芯片中，半导体存储器系统以及屏蔽写入数据，数据，命令和地址信号流的方法根据预定义的协议以信号帧的形式被串行发送。 半导体存储器系统和预定义协议适于将一个写入数据/命令流内的分别关联的写入数据单元的写入数据掩码位传送到紧密关系。 半导体存储器芯片的接收接口和存储器核心之间的接口部分包括帧解码器和中间数据缓冲器。

公开(公告)号：US06625065B2

公开(公告)日：2003-09-23

申请号：US09978399

申请日：2001-10-16

Applicant: Martin Gall ,  Andre Schaefer

Inventor： Martin Gall ,  Andre Schaefer

IPC: G11C700

CPC classification number: G11C11/4096 ,  G11C7/1006 ,  G11C7/1078

Abstract: A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

公开(公告)号：US09230614B2

公开(公告)日：2016-01-05

申请号：US13977404

申请日：2011-12-23

Applicant: Andre Schaefer ,  Ruchir Saraswat

Inventor： Andre Schaefer ,  Ruchir Saraswat

IPC: G11C5/14 ,  G11C7/00 ,  G11C11/4074 ,  G11C5/02 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C7/00 ,  G11C5/025 ,  G11C5/147 ,  G11C11/4074 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.

Abstract translation: 在堆叠式存储器架构中的分离的微通道电压域存储器件的一个实施例包括一个包括一个或多个耦合的存储器管芯的存储器堆栈，其中存储器堆叠的第一存储器管芯包括多个微通道，以及与存储堆栈耦合的逻辑芯片， 逻辑芯片包括存储器控制器。 每个微通道包括单独的电压域，并且为多个微通道中的每一个控制电压电平。

公开(公告)号：US09229466B2

公开(公告)日：2016-01-05

申请号：US13977460

申请日：2011-12-31

Applicant: Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

Inventor： Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

IPC: H01L27/06 ,  G05F1/618 ,  H02M3/156 ,  H01L25/065 ,  H01L27/02 ,  H01L49/02 ,  H01L23/48 ,  H01L23/64 ,  H01L25/18 ,  H01L23/522 ,  H02M7/00

CPC classification number: G05F1/618 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H02M3/156 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.

Abstract translation: 用于多堆叠集成电路中的一个或多个管芯的电压调节器包括位于管芯上的电感器，电耦合到电感器并且还位于管芯上的电压控制器，以及电耦合到 电感和电压控制器，也位于模具上。 电感器定义了内部空间，电压控制器和电容器位于电感器的内部空间内。 电感器可以是横向电感器或通过电感器的贯穿层。 多层集成电路可以具有多个管芯。 电压控制器可以电耦合到每个模具，尽管它可以仅位于一个模具上。 或者，单独的电压控制器可以电耦合到多个管芯中的每个，并且可以位于每个相应的管芯上。