公开(公告)号：EP0720079A1

公开(公告)日：1996-07-03

申请号：EP94830595.8

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Gnudi, Antonio

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal,
b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents,
c) a voltage generator (VG) connected between said two control terminals (G1, G2), and
d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals.

The output (OT) is coupled to one (G2) of said control terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少两个晶体管（M1，M2）分别具有两个控制端（G1，G2）并具有基本相同 所述两个晶体管（M1，M2）中的每一个也具有第一（S1，S2）和第二（D1，D2）主导体端子，b）具有至少两个输入输出端子的电流镜（MC） 所述两个端子（IM，OM）分别耦合到所述两个晶体管（M1，M2），以向它们提供偏置电流; c）电压发生器（VG），连接在所述两个控制端子 ，G2），以及d）所述控制端子（G1，G2）和所述输入 - 输出端子的一个（OM）之间的反馈路径（FP）。 输出（OT）耦合到所述控制端的一个（G2）。

公开(公告)号：EP0696839A1

公开(公告)日：1996-02-14

申请号：EP94830402.7

申请日：1994-08-12

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M3/07

Abstract: The present invention relates to a charge pump MOS voltage booster and to two applications where said type of booster can find advantageous use.
The voltage booster comprises instead of the classical diodes, which exhibit undesired voltage drop, four MOS transistors and, instead of the classical single-output oscillator with associated charge transfer condenser, an oscillator with two outputs and two corresponding charge transfer condensers.
In this manner there are practically no undesired voltage drops and the ripple is reduced without complicating the circuitry structure.

Abstract translation: 本发明涉及一种电荷泵MOS电压升压器和两种应用，其中所述类型的升压器可以发现有利的用途。 升压器包括代替典型的二极管，其表现出不希望的电压降，四个MOS晶体管，而不是经典的具有相关电荷转移电容器的单输出振荡器，具有两个输出的振荡器和两个相应的电荷转移电容器。 以这种方式，实际上没有不期望的电压降并且纹波减小而不使电路结构复杂化。 $$

公开(公告)号：EP0629001A1

公开(公告)日：1994-12-14

申请号：EP93830255.1

申请日：1993-06-10

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Palara, Sergio

IPC: H01L27/07 ,  H01L29/72

CPC classification number: H01L29/7802 ,  H01L27/0716 ,  H01L29/0878

Abstract: An integrated structure is described, that comprises a vertical bipolar transistor and a vertical MOSFET transistor, where, in order to reduce the series resistance of the MOSFET transistor, the collector region of the bipolar transistor and the drain region of the MOSFET transistor are both parts of a common zone and are contiguous each other, so that the high charge injection in the collector region when the bipolar transistor is in conduction state, causes a simultaneous increase in the conductivity of the drain region of the MOSFET transistor.
Both transistors are formed by cells each containing an elementary bipolar transistor and an elementary MOSFET transistor.

Abstract translation: 描述了一种集成结构，其包括垂直双极晶体管和垂直MOSFET晶体管，其中为了降低MOSFET晶体管的串联电阻，双极晶体管的集电极区域和MOSFET晶体管的漏极区域都是部分 并且彼此相邻，使得当双极晶体管处于导通状态时在集电极区域中的高电荷注入导致MOSFET晶体管的漏极区域的导电性的同时增加。 这两个晶体管由每个包含基本双极晶体管和基本MOSFET晶体管的单元形成。

公开(公告)号：EP0628903A1

公开(公告)日：1994-12-14

申请号：EP93830252.8

申请日：1993-06-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Russo, Baigio ,  Poluzzi, Rinaldo ,  Luzzi, Claudio

IPC: G06F1/035 ,  G06F15/76 ,  G06F7/60 ,  G05B13/02

CPC classification number: G06N7/04 ,  G05B13/0275 ,  G06F1/035 ,  Y10S706/90

Abstract: A method for setting up the memory of an electronic controller operates in Fuzzy logic, whereby predetermined membership functions (f(m)) of logic variables (M), defined within a universe of discourse (U) sampled in a finite number of points (m), are subjected to inference operations basically configured by IF/THEN rules with at least one front preposition and at least one rear implication. The controller further comprises a central control unit (3) provided with a memory section (5) for storing predetermined values (l) of the membership functions (f(m)) which appear in the front or IF part of the Fuzzy rules and have a predetermined degree (G) of truth or membership. This method provides for storing into said memory section (5) the only values (l) of those membership functions (f(m)) which have a value (l) of the degree of membership (G) other than zero at the points (m) of the universe of discourse (U),.

Abstract translation: 一种用于建立电子控制器的存储器中的方法操作中，因此，预定隶属功能的逻辑变量（M）的（F（M）），话语（U）的宇宙中定义在有限数量的点（采样模糊逻辑 米），经受由推理IF / THEN规则，至少一个前介词和至少一个后含义配置的基本操作。 所述控制器还包括设置有存储部（5）的中央控制单元（3），用于存储显示在前面或IF的模糊规则的一部分并具有隶属函数的预定值（升）（F（米）） 真相或会员的预定程度（G）。 该方法提供了用于存储到所述存储部（5）的那些隶属函数的唯一值（升）（F（M）），其具有会员资格的（G）比在点零以外的程度的值（L）（ 话语（U）的宇宙的米），。

公开(公告)号：EP0622849A1

公开(公告)日：1994-11-02

申请号：EP93830180.1

申请日：1993-04-28

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Palara, Sergio

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0255 ,  H01L27/0664 ,  H01L29/7808 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold, being formed on a chip of an N-semiconductor material, comprises a plurality of isolated N-regions (16a-c), each bounded laterally by an isolating region (15a-c) and at the bottom by two buried P- and N-regions which form in combination a junction with a predetermined reverse conduction threshold, and means (15a,18,17b,15b,17c) of connecting the junctions of the various isolated regions serially together in the same conduction sense; the buried N-region of the first junction (Z1) in the series is connected to a common electrode (C), which also is one terminal of the device, over an internal path (R) of the N-material of the chip, and the buried P-region of the last junction (Zn) in the series contains an additional buried N-region (14d) which is connected electrically to a second terminal (18a) of the device.

Abstract translation: （具有预定单向导通阈值的电子设备的结构，而形成n型半导体材料的芯片上，在隔离区15a-C包括分离的N-区（16a-c）中，每个有界尾盘反弹的多个由 ），并且在由两个底部掩埋P和N区域中组合，其形成具有预定反向导通阈值的结，并且装置（15a，18,17b，15b中，串联连接的各隔离区的连接处的17C） 一起在相同的导通感; 该系列中的第一个结（Z1）的掩埋N区域被连接到一个公共电极（C），因此所有这是该装置的一个终端，切换到芯片的N材料的内部路径（R）， 和该系列中的负载结（Zn）的的掩埋P区包含其电连接到所述装置的第二端（18A）附加掩埋N区（14D）所有。

公开(公告)号：EP0575686A1

公开(公告)日：1993-12-29

申请号：EP92830269.4

申请日：1992-05-27

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Imbruglia, Antonio ,  Benenati, Giovanni

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/01855 ,  H03K19/018585

Abstract: A CMOS logic circuit with biased inputs to a predetermined logic level, being of a type including at least one signal input (IN) and logic gates (4,5) for handling said signal, further includes a circuit portion (7) which is connected to the signal input (IN), and the equivalent of a high-value resistance effective to bias said input (IN).

Abstract translation: 具有偏置输入到预定逻辑电平的CMOS逻辑电路，其是包括用于处理所述信号的至少一个信号输入（IN）和逻辑门（4,5）的类型，还包括连接的电路部分（7） 到信号输入（IN），并且相当于有效偏置所述输入（IN）的高电阻值。

公开(公告)号：EP0740073B1

公开(公告)日：2004-08-18

申请号：EP95830168.1

申请日：1995-04-28

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Palara, Sergio ,  Sueri, Stefano ,  Schiaccianoce, Salvatore

IPC: F02P17/12 ,  G01R29/027 ,  G01R31/38

CPC classification number: H01T13/60 ,  F02P17/12 ,  G01R29/0273

公开(公告)号：EP0757511B1

公开(公告)日：2003-03-26

申请号：EP95830340.6

申请日：1995-07-31

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Palara, Sergio ,  Graziano, Vito

IPC: H05B41/00 ,  H03K17/687 ,  H02M7/5383 ,  H05B41/295

CPC classification number: H05B41/2825 ,  H02M7/5383 ,  H03K17/166 ,  H03K17/284

公开(公告)号：EP0680224B1

公开(公告)日：2002-11-13

申请号：EP94830196.5

申请日：1994-04-27

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Mancuso, Massimo ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: H04N9/64 ,  H04N5/21 ,  H04N5/44

CPC classification number: H04N7/012 ,  H03H2222/02 ,  H04N5/21 ,  H04N7/0132 ,  H04N9/646 ,  Y10S706/90

公开(公告)号：EP0809294B1

公开(公告)日：2002-01-02

申请号：EP96830293.5

申请日：1996-05-21

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Aiello, Natale ,  Patti, Davide ,  Scaccianoce, Salvatore ,  Leonardi, Salvatore

IPC: H01L27/00 ,  H01L27/082 ,  H01L21/8224

CPC classification number: H01L27/0821 ,  H01L21/8224