公开(公告)号：EP0720079B1

公开(公告)日：2004-09-29

申请号：EP94830595.8

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Gnudi, Antonio

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

公开(公告)号：EP0675431A1

公开(公告)日：1995-10-04

申请号：EP94830158.5

申请日：1994-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Abruzzese, Massimo ,  Giacalone, Biagio

IPC: G06F7/60

CPC classification number: G06N7/04 ,  Y10S706/90

Abstract: Memorization method in an electronic controller operating with fuzzy logic procedures for membership functions (FA) of logical variables (M) defined in a so-called discourse universe (U) discretized at a finite number of points (m) which provide memorization of triangular or trapezoid membership functions (FA) by means of memory words comprising a first portion in which is contained a codification of the vertex of the membership function (FA) and a second portion containing a codification corresponding to the slope of at least one side of the membership function (FA) as well as a third portion containing a codification corresponding to the slope of at least one other side of the function.

Abstract translation: 在以有限数量的点（m）分离的所谓的话语宇宙（U）中定义的逻辑变量（M）的隶属函数（FA）的模糊逻辑程序的记忆方法，其提供三角形或 借助于包含第一部分的存储单词的梯形隶属函数（FA），其中包含隶属函数（FA）的顶点的编码，以及包含对应于成员资格的至少一侧的斜率的编码的第二部分 功能（FA）以及包含对应于功能的至少另一侧的斜率的编码的第三部分。

公开(公告)号：EP0725328B1

公开(公告)日：2006-04-05

申请号：EP95830025.3

申请日：1995-01-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Giacalone, Biagio ,  Bruno, Dario ,  Matranga, Vincenzo ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  H03F3/30

CPC classification number: H03F3/3001 ,  G05F3/242 ,  G05F3/262

公开(公告)号：EP0725328A1

公开(公告)日：1996-08-07

申请号：EP95830025.3

申请日：1995-01-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Giacalone, Biagio ,  Bruno, Dario ,  Matranga, Vincenzo ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  H03F3/30

CPC classification number: H03F3/3001 ,  G05F3/242 ,  G05F3/262

Abstract: The present level shift circuit has a first (I1) and a second (I2) input respectively for input of a first and a second voltage signal and an output (OT) and comprises:

a) a first transistor (Q1) having a control terminal (G1), a first (S1) and a second (D1) main conduction terminal identifying a main conduction path, and
b) a second transistor (Q2) of the same type as said first transistor (Q1) and having a control terminal (G2), a first (S2) and a second (D2) main conduction terminal identifying a main conduction path.
The first signal is applied essentially between said control terminal (G1) and said first terminal (S1) of said first transistor (Q1) and said second input (I2) is coupled with the control terminal (G2) of said second transistor (Q2). The currents flowing in the conduction paths of the first (Q1) and the second (Q2) transistors are mutually proportional and one made from the other. The output (OT) is coupled with the first terminal (S2) of the second transistor (Q2). The control terminal (G1) of said first transistor (Q1) is connected to a potential reference (GND). The first signal is applied essentially to said first terminal (S1) of said first transistor (Q1).

Abstract translation: 当前电平移位电路分别具有用于输入第一和第二电压信号和输出（OT）的第一（I1）和第二（I2）输入，并且包括：a）具有控制端子的第一晶体管（Q1） （G1），识别主导通路径的第一（S1）和第二（D1）主导电端子，以及b）与所述第一晶体管（Q1）相同类型的第二晶体管（Q2），并具有控制端子 G2），识别主导电路径的第一（S2）和第二（D2）主导电端子。 第一信号基本上在所述控制端（G1）和所述第一晶体管（Q1）的所述第一端（S1）之间施加，而所述第二输入（I2）与所述第二晶体管（Q2）的控制端（G2）耦合， 。 在第一（Q1）和第二（Q2）晶体管的导通路径中流动的电流是相互成比例的，另一个是由另一个制成的。 输出（OT）与第二晶体管（Q2）的第一端子（S2）耦合。 所述第一晶体管（Q1）的控制端子（G1）连接到电位基准（GND）。 第一信号基本上应用于所述第一晶体管（Q1）的所述第一端子（S1）。

公开(公告)号：EP0675430A1

公开(公告)日：1995-10-04

申请号：EP94830157.7

申请日：1994-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Abruzzese, Massimo ,  Giacalone, Biagio

IPC: G06F7/60

CPC classification number: G06N7/04 ,  Y10S706/90

Abstract: Circuit for calculation of values of membership functions (FA) in a controller (1) operating with fuzzy logic procedures and said membership functions (FA) being of triangular or trapezoid form and defined in a so-called discourse universe (U) discretized in a finite number of points (m) and said controller (1) comprising a central control unit (3) equipped with a memory section (5) for memorization of said membership functions (FA) and connected to a microprocessor (9) in turn connected to an interface (13) and in which the membership functions (FA) are memorized by means of a codification (FA i ) of the coordinate of the vertex and the slopes at the sides of the vertex. The circuit comprises a calculator (11) connected to the memory section (5), to the microprocessor (9), and to the interface (13), to reconstruct the value (α) of each membership functions (FA) at each point of the discourse universe (U).

Abstract translation: 用于计算在模糊逻辑过程中操作的控制器（1）中的隶属函数（FA）的值的电路，并且所述隶属函数（FA）是三角形或梯形的并且在所谓的话语宇宙（U）中定义， 有限数量的点（m）和所述控制器（1）包括配备有用于存储所述隶属函数（FA）并连接到微处理器（9）的存储器部分（5）的中央控制单元（3），所述微处理器又连接到 接口（13），其中通过顶点坐标和顶点侧面的斜率的编码（FAi）来存储隶属函数（FA）。 电路包括连接到存储器部分（5），微处理器（9）和接口（13）的计算器（11），以重建每个隶属度函数（FA）的值（α） 话语宇宙（U）。

公开(公告)号：EP0720078A1

公开(公告)日：1996-07-03

申请号：EP94830593.3

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least one first (M1) and one second (M2) transistor of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT),
b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents,
c) a first (VDD) and a second (GND) potential reference, and
d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals.

The control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) and second (E2) end terminals respectively to said first (VDD) and second (GND) potential references.
The output (OT) is coupled to one (E1) of said end terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少一个第一（M1）和一个第二（M2）晶体管分别具有两个控制端（G1，G2） 并且具有与连接到恒定电位节点（IT）的所述第一晶体管（M1）的控制端子（G1）基本相同的阈值，b）具有至少一个输入端子（IM）和一个输出端的电流镜 端子（OM）分别耦合到所述第一（M1）和第二（M2）晶体管，以便向它们提供偏置电流，c）第一（VDD）和第二（GND）电位参考，以及d）分压器 （VD）具有中间抽头（E3）和第一（E1）和第二（E2）端子端子。 所述第二晶体管（M2）的控制端（G2）耦合到所述抽头（E3），并且所述分压器（VD）分别通过将所述第一（E1）和第二（E2）端子端分别耦合到所述第一（VDD） 和第二（GND）电位参考。 输出（OT）耦合到所述端子的一个（E1）。

公开(公告)号：EP0684550A1

公开(公告)日：1995-11-29

申请号：EP94830241.9

申请日：1994-05-23

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Matranga, Vincenzo ,  Giacalone, Biagio ,  Abruzzese, Massimo

IPC: G06F7/60

CPC classification number: G06N7/04

Abstract: Method of parallel processing of multiple inference rules (R) organised in fuzzy sets or logical functions of multiple fuzzy sets comprising membership functions (I') defined in a so-called universe of discourse (U) and said inference rules (R) being configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication and each preposition comprising at least one term (T) of comparison between membership functions (I') and a plurality of input data (I) and each term (T) being separated by logical operators (OL).
The method associates with the logical operators (OL) maximum and minimum operations among two or more elements and calculates exhaustively the overall degree of truth (Ω) of a rule (R) with a maximum or minimum of N partial truth levels (w).

Abstract translation: 在模糊集合或多个模糊集包含在话语中（U）和所述推理规则（R）的一个所谓的宇宙定义隶属函数（I“）的逻辑功能组织的多个推理规则（R）的并行处理方法被配置 基本上如IF-THEN与至少一个先行介词和至少一个随后的含义，并且每个介词包括隶属函数之间的比较中的至少一个术语（T）（I“）和输入数据（I）的多元的，每个术语的规则 （T）通过逻辑运算符（OL）分离。 一个规则（R）与N-局部真理水平的最大值或最小值（W）的与逻辑运算符（OL）的最大值和两个或多个元件，并且计算详尽之间最小限度的操作的方法相关联的真理（OMEGA）的整体程度。

公开(公告)号：EP0684549B1

公开(公告)日：2000-11-02

申请号：EP94830240.1

申请日：1994-05-23

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Giacalone, Biagio ,  Catania, Vincenzo ,  Luzzi, Claudio ,  Matranga, Vincenzo

IPC: G06F7/00

CPC classification number: G06N7/04 ,  Y10S706/90

公开(公告)号：EP0720079A1

公开(公告)日：1996-07-03

申请号：EP94830595.8

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Gnudi, Antonio

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal,
b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents,
c) a voltage generator (VG) connected between said two control terminals (G1, G2), and
d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals.

The output (OT) is coupled to one (G2) of said control terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少两个晶体管（M1，M2）分别具有两个控制端（G1，G2）并具有基本相同 所述两个晶体管（M1，M2）中的每一个也具有第一（S1，S2）和第二（D1，D2）主导体端子，b）具有至少两个输入输出端子的电流镜（MC） 所述两个端子（IM，OM）分别耦合到所述两个晶体管（M1，M2），以向它们提供偏置电流; c）电压发生器（VG），连接在所述两个控制端子 ，G2），以及d）所述控制端子（G1，G2）和所述输入 - 输出端子的一个（OM）之间的反馈路径（FP）。 输出（OT）耦合到所述控制端的一个（G2）。

公开(公告)号：EP0684550B1

公开(公告)日：2003-03-26

申请号：EP94830241.9

申请日：1994-05-23

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Matranga, Vincenzo ,  Giacalone, Biagio ,  Abruzzese, Massimo

IPC: G06N7/04

CPC classification number: G06N7/04