公开(公告)号：EP0720078B1

公开(公告)日：1999-04-28

申请号：EP94830593.3

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

公开(公告)号：EP0720079B1

公开(公告)日：2004-09-29

申请号：EP94830595.8

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Gnudi, Antonio

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

公开(公告)号：EP0740260B1

公开(公告)日：2001-08-22

申请号：EP95830170.7

申请日：1995-04-28

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60

CPC classification number: G06N7/043

公开(公告)号：EP0740260A1

公开(公告)日：1996-10-30

申请号：EP95830170.7

申请日：1995-04-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60

CPC classification number: G06N7/043

Abstract: The analog processor of this invention can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry.
To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs (AI) and outputs (OUT), and includes a biasing section (BIAS) which supplies voltage bias signals (VG), of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage.
This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator.
A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage. It follows that it may be advantageous to extract that reference voltage by division from a signal indicating the width of the input signal variation range, thereby to achieve compensation for or independence of variations of this range.

Abstract translation: 本发明的模拟处理器可以使用相当简单的电路以可靠的方式和高性能水平独立于工作温度和工艺参数进行处理。 为了实现这种独立性，处理器基本上实现并与MOS晶体管集成，具有电压输入（AI）和输出（OUT）两者，并且包括提供电压偏置信号（VG）的偏置部分（BIAS），其至少 一个基本上是与MOS晶体管的阈值电压成比例的电压和参考电压的总和。 可以从对温度和工艺参数稳定的参考电位提取该参考电压，例如由带隙型发生器产生的参考电压。 根据本发明的处理器的主要特征是其输入 - 输出特性相对于该参考电压的线性。 因此，通过从指示输入信号变化范围的宽度的信号中分离来提取参考电压可能是有利的，从而实现对该范围的变化的补偿或独立性。

公开(公告)号：EP0720079A1

公开(公告)日：1996-07-03

申请号：EP94830595.8

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Gnudi, Antonio

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal,
b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents,
c) a voltage generator (VG) connected between said two control terminals (G1, G2), and
d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals.

The output (OT) is coupled to one (G2) of said control terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少两个晶体管（M1，M2）分别具有两个控制端（G1，G2）并具有基本相同 所述两个晶体管（M1，M2）中的每一个也具有第一（S1，S2）和第二（D1，D2）主导体端子，b）具有至少两个输入输出端子的电流镜（MC） 所述两个端子（IM，OM）分别耦合到所述两个晶体管（M1，M2），以向它们提供偏置电流; c）电压发生器（VG），连接在所述两个控制端子 ，G2），以及d）所述控制端子（G1，G2）和所述输入 - 输出端子的一个（OM）之间的反馈路径（FP）。 输出（OT）耦合到所述控制端的一个（G2）。

公开(公告)号：EP0740261A1

公开(公告)日：1996-10-30

申请号：EP95830171.5

申请日：1995-04-28

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60 ,  G05F3/24

CPC classification number: G06N7/043 ,  G05F3/24

Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form.
It comprises a storage section (MEM) having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals (PP) on such outputs; the storage section (MEM) is input a plurality of supply voltage signals (VI) and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs.
Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches (SW) controlled by storage elements (E) are used in the storage section (MEM).

Abstract translation: 本发明的模拟处理器是可编程的并且能够以模拟形式存储处理系数。 它包括具有至少一个输出的存储部分（MEM），在大多数情况下多个输出，并且适于在这种输出上分别产生编程信号（PP）; 存储部分（MEM）输入多个电源电压信号（VI），并且可操作地结合存储在其中的信息产生每个输出上的电源电压信号中的一个，应当理解，一个电压信号可以 在几个这样的产出上产生。 有利地，如果在存储部分（MEM）中使用由存储元件（E）控制的开关（SW）），则处理器也可以以简单的方式从数字类型的电路编程。

公开(公告)号：EP0720078A1

公开(公告)日：1996-07-03

申请号：EP94830593.3

申请日：1994-12-30

Applicant: CO.RI.M.ME.

Inventor： Bruno, Dario ,  Giacalone, Biagio ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/262

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises:

a) at least one first (M1) and one second (M2) transistor of the same type having respectively two control terminals (G1,G2) and having essentially the same threshold with the control terminal (G1) of said first transistor (M1) connected to a constant potential node (IT),
b) a current mirror (MC) having at least one input terminal (IM) and one output terminal (OM) coupled respectively to said first (M1) and second (M2) transistors so as to supply to them the bias currents,
c) a first (VDD) and a second (GND) potential reference, and
d) a voltage divider (VD) having an intermediate tap (E3) and a first (E1) and a second (E2) end terminals.

The control terminal (G2) of said second transistor (M2) is coupled to said tap (E3) and said divider (VD) is biased by coupling said first (E1) and second (E2) end terminals respectively to said first (VDD) and second (GND) potential references.
The output (OT) is coupled to one (E1) of said end terminals.

Abstract translation: 根据本发明的晶体管阈值提取电路具有输出（OT），包括：a）相同类型的至少一个第一（M1）和一个第二（M2）晶体管分别具有两个控制端（G1，G2） 并且具有与连接到恒定电位节点（IT）的所述第一晶体管（M1）的控制端子（G1）基本相同的阈值，b）具有至少一个输入端子（IM）和一个输出端的电流镜 端子（OM）分别耦合到所述第一（M1）和第二（M2）晶体管，以便向它们提供偏置电流，c）第一（VDD）和第二（GND）电位参考，以及d）分压器 （VD）具有中间抽头（E3）和第一（E1）和第二（E2）端子端子。 所述第二晶体管（M2）的控制端（G2）耦合到所述抽头（E3），并且所述分压器（VD）分别通过将所述第一（E1）和第二（E2）端子端分别耦合到所述第一（VDD） 和第二（GND）电位参考。 输出（OT）耦合到所述端子的一个（E1）。

公开(公告)号：EP0725328B1

公开(公告)日：2006-04-05

申请号：EP95830025.3

申请日：1995-01-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Giacalone, Biagio ,  Bruno, Dario ,  Matranga, Vincenzo ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  H03F3/30

CPC classification number: H03F3/3001 ,  G05F3/242 ,  G05F3/262

公开(公告)号：EP0740261B1

公开(公告)日：2002-09-25

申请号：EP95830171.5

申请日：1995-04-28

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

IPC: G06G7/60 ,  G05F3/24

CPC classification number: G06N7/043 ,  G05F3/24

公开(公告)号：EP0725328A1

公开(公告)日：1996-08-07

申请号：EP95830025.3

申请日：1995-01-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Giacalone, Biagio ,  Bruno, Dario ,  Matranga, Vincenzo ,  Manaresi, Nicolò ,  Franchi, Eleonora

IPC: G05F3/24 ,  H03F3/30

CPC classification number: H03F3/3001 ,  G05F3/242 ,  G05F3/262

Abstract: The present level shift circuit has a first (I1) and a second (I2) input respectively for input of a first and a second voltage signal and an output (OT) and comprises:

a) a first transistor (Q1) having a control terminal (G1), a first (S1) and a second (D1) main conduction terminal identifying a main conduction path, and
b) a second transistor (Q2) of the same type as said first transistor (Q1) and having a control terminal (G2), a first (S2) and a second (D2) main conduction terminal identifying a main conduction path.
The first signal is applied essentially between said control terminal (G1) and said first terminal (S1) of said first transistor (Q1) and said second input (I2) is coupled with the control terminal (G2) of said second transistor (Q2). The currents flowing in the conduction paths of the first (Q1) and the second (Q2) transistors are mutually proportional and one made from the other. The output (OT) is coupled with the first terminal (S2) of the second transistor (Q2). The control terminal (G1) of said first transistor (Q1) is connected to a potential reference (GND). The first signal is applied essentially to said first terminal (S1) of said first transistor (Q1).

Abstract translation: 当前电平移位电路分别具有用于输入第一和第二电压信号和输出（OT）的第一（I1）和第二（I2）输入，并且包括：a）具有控制端子的第一晶体管（Q1） （G1），识别主导通路径的第一（S1）和第二（D1）主导电端子，以及b）与所述第一晶体管（Q1）相同类型的第二晶体管（Q2），并具有控制端子 G2），识别主导电路径的第一（S2）和第二（D2）主导电端子。 第一信号基本上在所述控制端（G1）和所述第一晶体管（Q1）的所述第一端（S1）之间施加，而所述第二输入（I2）与所述第二晶体管（Q2）的控制端（G2）耦合， 。 在第一（Q1）和第二（Q2）晶体管的导通路径中流动的电流是相互成比例的，另一个是由另一个制成的。 输出（OT）与第二晶体管（Q2）的第一端子（S2）耦合。 所述第一晶体管（Q1）的控制端子（G1）连接到电位基准（GND）。 第一信号基本上应用于所述第一晶体管（Q1）的所述第一端子（S1）。