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    Voice coil motor control circuit and method
    44.
    发明专利
    Voice coil motor control circuit and method 有权
    语音线圈电机控制电路及方法

    公开(公告)号：JP2005050519A

    公开(公告)日：2005-02-24

    申请号：JP2004265484

    申请日：2004-09-13

    Applicant: Cirrus Logic Inc ,  サーラス・ロジック・インコーポレーテッド

    Inventor： ROMANO PAUL M

    IPC: G11B5/596 ,  G11B5/54 ,  G11B21/12 ,  H02P25/06 ,  H02P5/00

    CPC classification number: G11B5/54

    Abstract: PROBLEM TO BE SOLVED: To provide a voice coil motor control circuit and a method. SOLUTION: The voice coil motor (VCM) control circuit (10) controls a motor operation to position a disk drive head and actuator arm assembly (202). A data processor (220) is continuously updated with the current position and relative radial velocity of the disk drive head (206) and actuator arm assembly (208). The data processor (220) provides signals to a digital-analog converter (DAC) of the VCM control circuit (10) representative of the amount of energy necessary to move the head and actuator arm assembly to a parking position from a current operating position. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种音圈电机控制电路及方法。 解决方案：音圈电机（VCM）控制电路（10）控制电动机操作以定位盘驱动头和致动器臂组件（202）。 数据处理器（220）以盘驱动头（206）和致动器臂组件（208）的当前位置和相对径向速度连续地更新。 数据处理器（220）向VCM控制电路（10）的数模转换器（DAC）提供代表将头部和致动器臂组件从当前操作位置移动到驻车位置所需的能量的量。 版权所有（C）2005，JPO＆NCIPI

    The system and method using a system-on-chip with a software cache
    45.
    发明专利
    The system and method using a system-on-chip with a software cache 审中-公开

    公开(公告)号：JP2004523051A

    公开(公告)日：2004-07-29

    申请号：JP2002578151

    申请日：2002-03-20

    Applicant: シーラス ロジック,インコーポレイテッドCirrus Logic,Inc.

    Inventor： グレゴリー アレン ノース，

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0886 ,  G06F12/0864 ,  G06F12/1045

    Abstract: 仮想アドレス（Ｎ−２１からのビット）のタグビットと複数のソフトキャッシュレジスタエントリ（ＴＡＧ０〜ＴＡＧ１５）のタグフィールドを比較し、各エントリは、仮想メモリ内の対応するキャッシュラインに対するインデックス（０〜１５）に関連付けられる。 キャッシュラインのためのキャッシュラインの大きさは、プログラム可能である。 仮想アドレスのタグビット（Ｎ−２１からのビット）がソフトキャッシュエントリの内の１つのタグフィールドに整合する場合、そこからのインデックス（０〜１５）が物理アドレスを生成するために選択される。 物理アドレスが、対応するメモリの内のソフトキャッシュ空間へのオフセット（７〜１０のビス）として選択されたインデックスを用いて生成される。
    【選択図】図１３

    DIFFERENTIAL PHASE ERROR DETECTOR, AND DIFFERENTIAL METHOD GENERATING A TRACKING ERROR SIGNAL BY DETECTING PHASE ERROR
    46.
    发明专利
    DIFFERENTIAL PHASE ERROR DETECTOR, AND DIFFERENTIAL METHOD GENERATING A TRACKING ERROR SIGNAL BY DETECTING PHASE ERROR 失效

    公开(公告)号：JPH11149649A

    公开(公告)日：1999-06-02

    申请号：JP22830698

    申请日：1998-08-12

    Applicant: CIRRUS LOGIC INC

    Inventor： FEYH GERMAN S ,  SPINO LOUIS ,  PAUL ROMANO ,  LARRY KING

    IPC: G11B7/085 ,  G11B7/09

    Abstract: PROBLEM TO BE SOLVED: To generate a position error signal independently of a frequency component of recorded data in a differential phase detector for an optical disk recording device. SOLUTION: One pair of diagonal signals S1 and S2 are generated by adding each quadrant A-D of a quadripartite detector. Phase offset among these diagonal signals indicate a position error of an image of a pit at a point of time at which a image of a pit passes through an optical detector. This position error is obtained by calculating a difference between positive correlation and negative correlation of diagonal signals S1 and S2 which are called as dual arm correlation(DAC). Then, Δ is correlation offset, L is correlation length. In a suitable actual mode, correlation of offset Δ is adjusted to be suitable so that correlation between S1 and S2 is made the maximum.

    CIRCUIT CONTROLLING POWER USED AMOUNT IN ELECTRONIC SYSTEM AND ITS METHOD
    47.
    发明专利
    CIRCUIT CONTROLLING POWER USED AMOUNT IN ELECTRONIC SYSTEM AND ITS METHOD 失效

    公开(公告)号：JPH10340129A

    公开(公告)日：1998-12-22

    申请号：JP53198

    申请日：1998-01-05

    Applicant: CIRRUS LOGIC INC

    Inventor： HILLMAN JOHN ,  COOKE CHRISTOPHER

    IPC: G06F1/04 ,  G06F1/32 ,  G06F9/30

    Abstract: PROBLEM TO BE SOLVED: To reduce an power consumption amount by a register by deciding a registers that do not take part in a processing cycle based on the analysis result of each microinstruction and preventing them from being clocked in a processing cycle. SOLUTION: A decode logic 28 examines an appropriate field or a bit position of a microinstruction which is a set of all kinds of bits that control each processing cycle and decides which register 20 takes parts in a certain processing cycle. As for a register 20 which is decided as not taking part in the processing cycle here, a clock signal from a clock source 24 is blocked and the clock signal is prevented from adding to a clock input 21 of the register 20 through a corresponding AND gate 26. That makes it possible to reduce the total used amount of power in a system by reducing the power consumption of an unused register in a certain processing cycle from the power consumption of used registers.

    SERVO DECODER
    48.
    发明专利
    SERVO DECODER 失效

    公开(公告)号：JPH10283743A

    公开(公告)日：1998-10-23

    申请号：JP1625198

    申请日：1998-01-28

    Applicant: CIRRUS LOGIC INC

    Inventor： RICHARD T BEHRENS ,  ZOOK CHRISTOPHER P ,  STEVEN A TARKE ,  REED DAVID E

    IPC: G11B5/55 ,  G11B5/596 ,  G11B7/007 ,  G11B21/08 ,  G11B21/10 ,  G11B27/30

    Abstract: PROBLEM TO BE SOLVED: To enable a servo code format for a high recording density by mapping the detected code word of adjacent tracks to the decoded code word indicating one adjacent track at the time of mapping two detected code words to one decoded code word to seek the selected track with a read head. SOLUTION: This decoder 84 performs the decoding to an effective track address of estimated data sequence even when a readout signal becomes ambiguous due to interference between tracks during the seek operation. That is, a binary track address is coded depending on the coding scheme for correcting random bit error and ambiguity generated as a result of interference between tracks during the seek operation can be solved to overcome the limitation on the servo gray code. After the correction, seven code word bits is mapped to the four information bits in order to decode the code word.

    OBJECT REFERENCE MEMORY MAPPING
    49.
    发明专利
    OBJECT REFERENCE MEMORY MAPPING 失效

    公开(公告)号：JPH10116176A

    公开(公告)日：1998-05-06

    申请号：JP16723197

    申请日：1997-06-24

    Applicant: CIRRUS LOGIC INC

    Inventor： LARSON MICHAEL KERRY

    IPC: G06F3/153 ,  G06T11/20 ,  G06T15/80

    Abstract: PROBLEM TO BE SOLVED: To reduce the total frequency of access to a memory and its necessary time and then make the system fast by increasing the number of pixels which are plotted by single access. SOLUTION: A polygon plotting command refers to specific information regarding a polygon to be plotted (301) and determines XY high-speed memory segment size (303). Namely, the use efficiency of a high-speed memory is optimized, a part where a polygon is present is plotted by using high-speed sequential access, and a pixel write mask is used to determine which pixel is displayed on the screen of a display device by writing it in a pixel grid or frame buffer from the high-speed sequential access memory. Right after the segment size is determined, a segment is written in a high-speed sequential memory such as an SRAM and the segment is stored (305 and 307). Then it is decided whether or not polygon plotting corresponding to a polygon plotting command is completed (309).

    PARALLEL MULTIPLICATION INTEGRATING ARRAY CIRCUIT
    50.
    发明专利
    PARALLEL MULTIPLICATION INTEGRATING ARRAY CIRCUIT 失效

    公开(公告)号：JPH1097517A

    公开(公告)日：1998-04-14

    申请号：JP17466197

    申请日：1997-06-30

    Applicant: CIRRUS LOGIC INC

    Inventor： OGLETREE THOMAS

    IPC: G06F17/10 ,  G06F7/544

    Abstract: PROBLEM TO BE SOLVED: To speed up an operation processing shown by the form of the sum of products by providing a first multiplexer (MUX) giving 2x bit product output and a second multiplexer having output supplying one calculated value. SOLUTION: An inner control circuit 380 receives a discrete operation control value and a BM state control signal from BMMC devices 310-315. The inner control circuit 380 selects i-th input of first MUX 320 corresponding to a booth multiplier BMi by using a first MUX selection bus 382. A PMAA circuit 200 contains second MUX 370. Second MUX 370 has m=four inputs and respective inputs are connected to receive an output signal from one of four accumulator registers 360-363. An outer controller controls the selection bus 371 of second MUX 370 so that the output of ACCI being one of the accumulator registers 360-363 is selected and supplied j-th input of second MUX 370 is selected, and it is outputted through second MUX 370.

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