公开(公告)号：WO2022245607A2

公开(公告)日：2022-11-24

申请号：PCT/US2022/028744

申请日：2022-05-11

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GREENE, Jonathan W. ,  BARAJAS, Gabriel ,  LI, Fei ,  HASSAN, Hassan ,  TANDON, James Sumit

IPC: G06F30/367 ,  G06F119/12 ,  G06F2119/12 ,  G06F30/34 ,  G06F30/347

Abstract: A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.

公开(公告)号：WO2022231733A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/021525

申请日：2022-03-23

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： NORRIE, Christopher I. W.

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

公开(公告)号：WO2022191907A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/011022

申请日：2022-01-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： LANGER, Tamir ,  JACUBOVSKI, Migel

IPC: H01L27/02 ,  G01K3/04 ,  G01K7/01

Abstract: A method (50, 70, 600) provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed (51), each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled (52) to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated (53) over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared (54) to a threshold value. An action related to the thermal protection function is initiated (55) upon the integration output of an affected component exceeding the threshold value.

公开(公告)号：WO2021242303A1

公开(公告)日：2021-12-02

申请号：PCT/US2020/063289

申请日：2020-12-04

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： SELWAN, Pierre

IPC: G06F11/16

Abstract: A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.

公开(公告)号：WO2021145907A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/021542

申请日：2020-03-06

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GENDRON-HANSEN, Amaury ,  ODEKIRK, Bruce

IPC: H01L21/265 ,  H01L21/329 ,  H01L21/336 ,  H01L29/872 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02274 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/02579 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/67075 ,  H01L27/0927 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802

Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.

公开(公告)号：WO2015153101A3

公开(公告)日：2015-10-08

申请号：PCT/US2015/020563

申请日：2015-03-13

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： LYNCH, Scott

IPC: H05B33/08 ,  G05F1/56

Abstract: Employed within an LED driver (600) operating from the AC power line (120), the invention controls both input current and output power. With the regulation circuit (610, 620) desribed, input current appears purely resistive, precisely tracking the input voltage waveshape. At the same time, it provides good line regulation and inherent phase dimmer compatibility, requiring no special circuitry to detect and handle a dimmer.

公开(公告)号：WO1998024015A1

公开(公告)日：1998-06-04

申请号：PCT/US1997007241

申请日：1997-04-11

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  SUSAK, David, M. ,  THOMSEN, Joseph, A.

IPC: G05F01/40

CPC classification number: H02M1/36 ,  G05F3/24 ,  G05F3/242 ,  G05F3/262 ,  Y10S323/901

Abstract: A zero-current start-up circuit (20) for a reference circuit (22) which is initially unbiased and which has internal nodes that need to be regulated to a predetermined voltage. When the start-up circuit (20) is enabled, a switching transistor (36) is turned on which enables the reference circuit (22) to generate an internal reference current which regulates an output current to a predetermined value set by the reference circuit (22). The output current flows through a voltage drop device (40 and 42) and when the voltage level reaches a predetermined value, the start-up circuit (20) is disabled eliminating the current path.

Abstract translation: 一种用于参考电路（22）的零电流启动电路（20），其最初是无偏置的并且具有需要调节到预定电压的内部节点。 当启动电路（20）使能时，开关晶体管（36）导通，使得参考电路（22）能够产生将输出电流调节到由参考电路设置的预定值的内部参考电流（ 22）。 输出电流流经电压降装置（40和42），并且当电压电平达到预定值时，禁止启动电路（20）消除电流通路。

公开(公告)号：WO1997049085A1

公开(公告)日：1997-12-24

申请号：PCT/US1997006531

申请日：1997-04-12

Applicant: MICROCHIP TECHNOLOGY, INC.

Inventor： MICROCHIP TECHNOLOGY, INC. ,  BRUWER, Frederick, J. ,  VAN ROOYEN, Emile ,  SMIT, William ,  SALT, Thomas, C.

IPC: G11C07/00

CPC classification number: G11C16/225 ,  G11C5/141

Abstract: The present invention relates to a fail-safe non-volatile memory programming system. The system uses a high voltage charging capacitor (16) to store a charge for programming a memory device. A second charging capacitor (30) is used for supplying power to the control logic (26) used for programming the memory device. If power is removed during a programming cycle, the charge stored in the two capacitors is sufficient to complete the programming cycle.

Abstract translation: 本发明涉及故障安全非易失性存储器编程系统。 该系统使用高压充电电容器（16）来存储用于对存储器件进行编程的电荷。 第二充电电容器（30）用于向用于编程存储器件的控制逻辑（26）供电。 如果在编程周期中断电，则存储在两个电容器中的电荷足以完成编程周期。

公开(公告)号：US12175363B2

公开(公告)日：2024-12-24

申请号：US17089891

申请日：2020-11-05

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06N3/08 ,  G06F3/06 ,  G06N3/04 ,  G06N5/04 ,  G06N20/00 ,  G11C11/54 ,  G11C16/26

Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

公开(公告)号：US11843393B2

公开(公告)日：2023-12-12

申请号：US17952240

申请日：2022-09-24

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/611

Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.