公开(公告)号：EP1693957A1

公开(公告)日：2006-08-23

申请号：EP06250380.0

申请日：2006-01-24

Applicant: Renesas Technology Corp.

Inventor： Kyu, Irei c/o Hitachi Ltd., Intellectual P. Group ,  Tanaka, Satoshi c/o Hitachi Ltd., Int. P. Group ,  Maeda, Kouji c/o Hitachi Ltd., Int. P. Group ,  Akamine, Yukinori c/o Hitachi Ltd., Int. P. Group

IPC: H03F3/19

CPC classification number: H03F3/1935 ,  H03F3/19 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H04B1/0053 ,  H04B1/0458

Abstract: A multi-band radio module for selectively supplying received signals in a plurality of frequency bands to a low noise amplifier via an input impedance matching circuit by switching over the operation mode of the low noise amplifier is comprised of : a pre-stage amplification unit including a plurality of fundamental amplifiers connected to one another in parallel, the fundamental amplifiers sharing a load impedance connected to a source voltage and a grounded degeneration impedance and having input signal lines commonly connected to an input impedance matching circuit; a post-stage amplifier to which the output signals of the plurality of fundamental amplifiers are commonly inputted; and a bias control unit for selectively turning on the fundamental amplifiers, wherein the input impedance of the low noise amplifier is selectively optimized for the matching circuit depending on the RF band to be received.

Abstract translation: 一种用于通过切换低噪声放大器的操作模式经由输入阻抗匹配电路将多个频带中的接收信号选择性地提供给低噪声放大器的多频带无线电模块包括：前级放大单元，包括 并联连接的多个基本放大器，所述基本放大器共用连接到源电压和接地退化阻抗的负载阻抗，并具有共同连接到输入阻抗匹配电路的输入信号线; 通常输入多个基本放大器的输出信号的后级放大器; 以及用于选择性地接通基本放大器的偏置控制单元，其中根据要接收的RF频带，对于匹配电路，低噪声放大器的输入阻抗被选择性地优化。

公开(公告)号：EP1304731B1

公开(公告)日：2006-08-02

申请号：EP02705296.8

申请日：2002-03-18

Applicant: Canon Anelva Corporation ,  ULVAC, INC. ,  Kanto Denka Kogyo CO., LTD. ,  SANYO ELECTRIC CO., LTD. ,  SONY CORPORATION ,  DAIKIN INDUSTRIES, LTD. ,  TOKYO ELECTRON LIMITED ,  NEC Electronics Corporation ,  Hitachi Kokusai Electric Inc. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  MITSUBISHI DENKI KABUSHIKI KAISHA ,  Renesas Technology Corp.

Inventor： SHIBATA, Koji,c/o Research Institute of Innovative ,  TSUJI, Naoto, RES. I. OF INN. TECH. FOR THE EARTH ,  MURATA, Hitoshi, RES.I. OF INN.TECH. FOR THE EARTH ,  WANI, Etsuo, RES. INS. OF INN. TECH. FOR THE EARTH ,  KOSANO, Yoshihide, R. I. OF INN. T. FOR THE EARTH

IPC: H01L21/31 ,  C23C16/44 ,  H01L21/3065

CPC classification number: C23C16/4405 ,  Y10S134/902 ,  Y10S438/905

Abstract: A method of cleaning in a CVD device capable of efficiently removing by-products such as SiO2 and Si3N4 attached to and deposited on the inner wall of a reaction chamber and the surfaces of an electrode when forming films, being very low in cleaning gas exhaust amount, affecting very little environments such as global warming, and contributing to cost reduction. After films are formed on a substrate by a CVD device, a fluorine-containing compound-containing fluorine-based cleaning gas is turned into plasma by a remote plasma generator , the plasma-based cleaning gas is introduced into a reaction chamber, and by-products deposited on the inside of the reaction chamber are removed.

公开(公告)号：EP1480161A2

公开(公告)日：2004-11-24

申请号：EP04291257.6

申请日：2004-05-17

Applicant: SANWA DENKI KOGYO CO., LTD. ,  Renesas Technology Corp.

Inventor： Katsumata, Akira c/o Sanwa Denki Kogyo Co., Ltd ,  Nishizawa, Hirotaka c/o Renesas Technology Corp. ,  Osawa, Kenji c/o Renesas Technology Corp.

IPC: G06K17/00 ,  H05K5/00

CPC classification number: H05K5/0282 ,  G06K19/077 ,  G06K19/07732 ,  G06K19/07739

Abstract: An adapter for a memory card having a frame metal fitting to which an end portion of the card is inserted, whereby the card is detachably fitted, and a resin-molded body core assembled in the frame metal fitting by insertion, wherein an entire thickness of the adapter being approx. the same as that of the card, the frame metal fitting having a pair of holding portions in an approx. ⊐ shape in both end portions on the side of the card attached to hold both sides of the card, a hook portion between a pair of the holding portions being detachably engaged with the end portion of the card by spring force to prevent the card from coming off, a caulking projection fixing the core by caulking to the core, and an insulative coating film formed on the outer surface of the frame metal fitting.

Abstract translation: 一种用于存储卡的适配器，具有框架金属配件，卡片的端部插入该框架金属配件，由此可拆卸地安装卡片，以及通过插入组装在框架金属配件中的树脂成型体芯体，其中， 适配器约为 与卡的相同，框架金属配件具有一对保持部分， 在安装卡片两侧的卡的两侧的两端部的Š 形状，一对保持部之间的钩部分通过弹簧力与卡的端部可拆卸地接合，以防止卡 脱落，通过铆接固定到芯上的铆接突起，以及形成在框架金属配件的外表面上的绝缘涂膜。

公开(公告)号：EP1477990A1

公开(公告)日：2004-11-17

申请号：EP02700624.6

申请日：2002-02-20

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co.,Ltd.

Inventor： MIYAZAKI, Shinya, HITACHI ULSI SYSTEMS CO., LTD. ,  KATOH, Kei, HITACHI CLTD. ,  YAMAUCHI, Koudoh, HITACHI ULSI SYSTEMS CO., LTD.

IPC: G11C17/14 ,  H01L27/10

CPC classification number: G11C16/28 ,  G11C17/12 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115

Abstract: A semiconductor integrated circuit has over one semiconductor substrate a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines (bl and blb), word lines (wl_n), and memory cells (20). The memory cell comprises MOS transistors (M1 and M2) whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line (cs) or floated. During the other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Therefore, subthreshold leakage current is prevented from being passed through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.

Abstract translation: 半导体集成电路具有在一个半导体衬底上的非易失性存储器和使用存储在非易失性存储器中的信息来执行逻辑操作的逻辑电路。 非易失性存储器包括位线（bl和blb），字线（wl_n）和存储单元（20）。 存储器单元包括其栅电极与字线连接的MOS晶体管（M1和M2）。 根据MOS晶体管的一个源极/漏极是与源极线（cs）连接还是浮置来进行信息存储。 在访问存储单元的操作中的预定时间段以外的其他时间段期间，构成存储单元的MOS晶体管的源极/漏极电极之间的电位差被置零。 因此，防止亚阈值漏电流通过处于待机状态的存储单元。 在访问操作的预定时段期间，在MOS晶体管的源极/漏极之间产生电势差。 因此，位线电势可以通过字线选择而改变。

公开(公告)号：EP1444778A2

公开(公告)日：2004-08-11

申请号：EP02779678.8

申请日：2002-11-13

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： OKASAKA, Akira,S.&I. Circuits,Hitachi, Ltd ,  YAHAGI, Koichi,S.&I. Circuits,Hitachi, Ltd ,  SAKAGAMI, Masakazu,S.&I. Circuits,Hitachi, Ltd ,  HENSHAW, Robert Astle,TTPCOM Ltd

IPC: H03G3/00

CPC classification number: H03G3/3078

Abstract: A communication semiconductor integrated circuit device (200) includes an amplifier circuit (330) including a plurality of variable-gain amplifiers (PGA1-PGA3) for amplifying a received signal and a plurality of filter circuits (LPF1-LPF3), the amplifiers and the filter circuits being connected to each other in a multi-stage configuration, and a last amplifier (FFGA) having a gain set regardless of a level of a received signal and a filter circuit, the last amplifier and the filter circuit are disposed at the last stage of the amplifier circuit. The amplifier circuit has an amplification factor variable according to a level of a received signal. The communication semiconductor integrated circuit device further includes a plurality of offset correction circuits (OFC1-0FC4) for correcting direct-current offset.corresponding to the variable-gain amplifiers and the last amplifiers. respectively.The offset correction circuit (OFC4) corresponding to the last amplifierconducts an offset correction at a timing different from timing for the other offset correction circuits (OFCl-OFC3).

公开(公告)号：EP1429227A2

公开(公告)日：2004-06-16

申请号：EP03257713.2

申请日：2003-12-09

Applicant: Renesas Technology Corp.

Inventor： Okuda, Yuichi C/o Renesas Techn. Corp.

IPC: G06F1/00

CPC classification number: H01L23/576 ,  G06K19/073 ,  G06K19/07372 ,  G11C11/412 ,  G11C11/4125 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously. Reverse engineering by irradiation with light can be effectively prevented.

Abstract translation: 提供一种能够防止卡黑入侵的半导体集成电路，通过这种半导体集成电路非法获取由光的照射和被保护的秘密信息主动引起的错误动作。 由标准逻辑处理配置的光电检测器安装在诸如IC卡微计算机的半导体集成电路上，与其他电路几乎不区分并且消耗很少的待机功率。 例如，每个光电检测器具有这样的构造，其中第一状态通过其初始化动作保持在静态锁存器中，并且当处于非导通状态的半导体元件构成静态锁存器时，发生反转到第二状态 第一个状态被光照射。 多个光电检测器被布置在存储单元阵列中。 通过将静态锁存型光电检测器结合到存储器阵列中，它们可以不明显地排列。 可以有效地防止用光照射进行逆向工程。

公开(公告)号：EP1416540A1

公开(公告)日：2004-05-06

申请号：EP02749325.3

申请日：2002-07-22

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co.,Ltd.

Inventor： TANAKA, Toshihiro c/o Semicond.& Integr. Circuits ,  UMEMOTO, Yukiko c/o Semicond.& Integr. Circuits ,  HIRAKI, Mitsuru c/o Semicond.& Integr. Circuits ,  SHINAGAWA, Yutaka c/o HITACHI ULSI SYST CO., LTD. ,  FUJITO, Masamichi c/o HITACHI ULSI SYST.CO., LTD. ,  SUZUKAWA, Kazufumi c/o HITACHI ULSI SYST.CO.,LTD. ,  TANIKAWA, Hiroyuki c/o Semicond.& Integr. Circ. ,  YAMAKI, Takashi c/o Semicond.& Integr. Circuits ,  KAMIGAKI, Yoshiaki c/o Central Research Lab. ,  MINAMI, Shinichi c/o Semicond.& Integr. Circuits ,  KATAYAMA, Kozo c/o Semicond. & Integr. Circuits ,  MATSUZAKI, Nozomu c/o Central Research Laboratory

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：EP1608007B1

公开(公告)日：2012-08-15

申请号：EP04721668.4

申请日：2004-03-18

Applicant: HORIBA, LTD. ,  Renesas Technology Corp. ,  ROHM CO., LTD.

Inventor： TOMINAGA, Koji c/o Horiba, Ltd. ,  YASUDA, T. Nat. Inst. of AdvancedInd. Science and ,  NABATAME, Toshihide c/o Renesas Technology Corp. ,  IWAMOTO, Kunihiko c/o Rohm Co., Ltd.

IPC: H01L21/316 ,  H01L21/318 ,  C23C16/56 ,  C23C16/455 ,  H01L21/3105 ,  H01L21/314 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/28185 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/314 ,  H01L29/517

Abstract: A method for manufacturing a semiconductor device is disclosed which enables to eliminate impurities in a gate insulating film as much as possible which impurities deteriorate the film properties of the gate insulating film. In this method, a step for forming an insulating film with a thickness of 0.3-2 nm and a step for removing impurities in the insulating film are repeated a plurality of times, thereby forming an insulating film having a certain thickness.

公开(公告)号：EP1883041B1

公开(公告)日：2012-06-20

申请号：EP06746547.6

申请日：2006-05-17

Applicant: Sony Corporation ,  Renesas Technology Corp.

Inventor： AOKI, Yoshitaka ,  TSUTSUI, Keiichi ,  NISHIZAWA, Hirotaka, c/o RENESAS TECHNOLOGY CORP. ,  TOTSUKA, Takashi, c/o RENESAS TECHNOLOGY CORP.

IPC: G06K19/07 ,  G06F3/08 ,  G06K17/00

CPC classification number: G06K19/07 ,  G06K19/07732

Abstract: A memory card is used by selecting a plurality of interfaces. The memory card (100) is provided with a storage section (22) embedded in a holder (20); a controller (24) embedded in the holder; a plurality of first contacts (2-10) connected to the controller; a switching signal generating section (26) embedded in the holder; and two second contacts (11, 12) connected to the switching signal generating section. The switching signal generating section supplies an interface section (2402) with a switching signal (S1) corresponding to interface selection signals (D1, D2) fed through the second contact. Based on the interface selection signal (S1) fed through the second contact, one interface is selected from two types of interfaces and data communication is performed.

公开(公告)号：EP2051370A3

公开(公告)日：2010-06-09

申请号：EP08253219.3

申请日：2008-10-02

Applicant: Renesas Technology Corp.

Inventor： Shimamoto, Kenichi ,  Namie, Hisanori

IPC: H03F1/02

CPC classification number: H03F1/0216 ,  H03F3/24 ,  H03F2200/408 ,  H03F2200/451 ,  H03F2200/504 ,  H03F2200/78

Abstract: The RF power amplifier apparatus has an RF power amplifier (RFPA) and a power-supply circuit (Pwr_Cnt). The power-supply circuit controls the level of a source voltage (V LDO ) supplied to the RF power amplifier in response to the level of a power-control signal (Vapc). A sensing resistance (Rsen) produces a sense signal (Vsen) corresponding to a source current (I LDO ) with respect to a source voltage. A current-control unit (Cmp1,Cmp2,FF1,NAND3 and Qp4) controls the source current (I LDO ) in response to the sense signal (Vsen). When Vsen coincides with an allowable sense signal level (Vsh) corresponding to a source current allowable level I LDO (Max), the current-control unit controls the source current (I LDO ) to a limit current smaller than the allowable level I LDO (Max). Preferably, the limit current is a shutdown current when a shutdown switch is in OFF state. Thus, the drain of the battery of a mobile-phone terminal can be reduced even when an impedance mismatch condition lasts for a long time.