公开(公告)号：KR1020140080019A

公开(公告)日：2014-06-30

申请号：KR1020120149348

申请日：2012-12-20

Applicant: 삼성전기주식회사

Inventor： 박민철 ,  박상수 ,  안영규 ,  이병화

IPC: H01G4/12 ,  H01G4/30 ,  H01G2/06

CPC classification number: H01G4/12 ,  H01G2/06 ,  H01G4/012 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: Provided is a multilayered ceramic capacitor comprising: a ceramic body having multiple dielectric layers laminated therein; an active layer including multiple internal electrodes having the dielectric layers interposed therebetween to form capacitance and alternately exposed through respective end surfaces of the ceramic body; an upper cover layer formed above the active layer; a lower cover layer formed below the active layer and being thicker than the upper cover layer; and external electrodes covering both end surfaces and some parts of top and bottom surfaces of the ceramic body, wherein, when E is defined as the shortest distance from an end of an internal electrode disposed at the lowermost portion of the active layer to an end of an external electrode covering a part of the bottom surface of the ceramic body, T is defined as the shortest distance from the end of said external electrode to said internal electrode at the lowermost portion of the active layer, and F is defined as a margin portion in a length direction of the ceramic body, 1.2

Abstract translation: 提供一种多层陶瓷电容器，其包括：层叠有多个电介质层的陶瓷体; 包括多个内部电极的有源层，其间插入介电层以形成电容，并交替地通过陶瓷体的各个端面露出; 形成在有源层上方的上覆盖层; 在所述有源层下面形成并且比所述上覆盖层更厚的下覆盖层; 以及外部电极，其覆盖陶瓷体的两个端面和顶面和底面的一部分，其中，当E被定义为从设置在有源层的最下部分的内部电极的端部到端部的最短距离 覆盖陶瓷体的底面的一部分的外部电极T被定义为在有源层的最下部从所述外部电极的端部到所述内部电极的最短距离，并且F被定义为边缘部分 在陶瓷体的长度方向上，满足1.2 <= E / T且30μm<= F。

公开(公告)号：KR1020140076764A

公开(公告)日：2014-06-23

申请号：KR1020120145169

申请日：2012-12-13

Applicant: 삼성전기주식회사

Inventor： 박상수 ,  박민철 ,  안영규 ,  이병화

IPC: H01G4/12 ,  H01G4/30 ,  H01G2/06

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

Abstract: The present invention includes: a ceramic body in which multiple dielectric layers are stacked; an active layer which forms a capacity by including multiple first and second internal electrodes which are formed in order to be alternately exposed through both cross sections of the ceramic body across the dielectric layer; an upper cover layer which is formed in the upper part of the active layer; a lower cover layer which is formed in the lower part of the active layer and has a thickness which is thicker than the upper cover layer; and first and second external electrodes which are formed to cover the both cross sections of the ceramic body. In the provided multilayer ceramic capacitor, BW/I satisfies a range of 0.105

Abstract translation: 本发明包括：堆叠多个电介质层的陶瓷体; 通过包括形成多个第一和第二内部电极而形成容量的有源层，以便通过陶瓷体的两个横截面交替地暴露在电介质层上; 形成在有源层的上部的上覆盖层; 下覆盖层，其形成在有源层的下部，并且具有比上覆盖层更厚的厚度; 以及形成为覆盖陶瓷体的两个截面的第一和第二外部电极。 在提供的多层陶瓷电容器中，当定义陶瓷体的上长度，中长度和下限之间的平均值时，BW / I满足0.105 <= BW / I <= 1.049的范围，因为I和总和的平均值 第一外部电极的上长度，中长度和下限以及第二外部电极的上长度，中长度和下限为BW。

公开(公告)号：KR1020140073644A

公开(公告)日：2014-06-17

申请号：KR1020120139624

申请日：2012-12-04

Applicant: 삼성전기주식회사

Inventor： 박민철 ,  박상수 ,  안영규 ,  이병화

IPC: H01G4/12 ,  H01G4/30 ,  H01G2/06

CPC classification number: H01G4/002 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

Abstract: The present invention provides a multi-layered ceramic capacitor. The multi-layered ceramic capacitor includes: a ceramic body in which a plurality of dielectric layers with an average thickness of 0.2 to 2.0 μm is multi-layered; an active layer which forms capacitance by including a plurality of first and second internal electrodes which are formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layers interposed between the first and second internal electrodes; an upper cover layer; an upper cover layer formed on an upper part of the active layer; a lower cover layer formed on a lower part of the active layer, and having a thickness thicker than that of the upper cover layer; and first and second external electrodes formed to cover both end surfaces of the ceramic body, wherein the dielectric layer consists of dielectric grains, and wherein Da

Abstract translation: 本发明提供一种多层陶瓷电容器。 多层陶瓷电容器包括：多层平均厚度为0.2〜2.0μm的多个电介质层的陶瓷体; 活性层，其通过包括多个第一和第二内部电极形成电容，所述第一和第二内部电极形成为交替地暴露于陶瓷体的两个端面，其中介电层插入在第一和第二内部电极之间; 上盖层; 形成在有源层的上部的上覆盖层; 形成在所述有源层下部的厚度比所述上覆盖层厚的厚的下覆层; 以及形成为覆盖陶瓷体的两个端面的第一外部电极和第二外部电极，其中介电层由电介质晶粒构成，并且其中当Da <= td / 3和0.2μm

公开(公告)号：KR1020140038876A

公开(公告)日：2014-03-31

申请号：KR1020130095952

申请日：2013-08-13

Applicant: 삼성전기주식회사

Inventor： 이교광 ,  김진 ,  안영규 ,  이병화

IPC: H01G4/12 ,  H01G4/30 ,  H01G2/06

Abstract: The present invention comprises: a ceramic body on which a plurality of dielectric layers are laminated in a width direction; a first and a second inner electrode arranged by turns with the dielectric layers as the center; a first and a second lid part extended and exposed to the bottom surface of the ceramic body apart from the first inner electrode in a longitude direction; a third lid part extended and exposed to the bottom surface of the ceramic body from the second inner electrode, arranged between the first and second lid parts; a first and second outer electrode connected to the first and second lid parts respectively, formed apart from each other on the bottom surface of the ceramic bodyl and a third outer electrode connected to the third lid part, extended to a part of two sides of the bottom surface of the ceramic body, arranged between the first and second outer electrodes. When a height on one side of the ceramic body among the third electrodes is considered ′d′, and the thickness of the ceramic body is considered ′T′, the rate between ′d′ and ′T′; is 0.10

Abstract translation: 本发明包括：在宽度方向上层叠有多个电介质层的陶瓷体; 以电介质层为中心配置的第一和第二内部电极; 第一和第二盖部分在经度方向上延伸并暴露于陶瓷体的离开第一内部电极的底表面; 第三盖部分，布置在第一和第二盖部分之间，从第二内部电极延伸并暴露于陶瓷体的底部表面; 第一外部电极和第二外部电极分别连接到第一和第二盖子部分，它们彼此分开形成在陶瓷基底的底表面上，第三外部电极连接到第三盖部分，延伸到第二盖子的两侧的一部分 设置在第一和第二外部电极之间的陶瓷体的底面。 当第三电极中的陶瓷体的一侧的高度被认为是'd'时，陶瓷体的厚度被认为是'T'，'d'和'T'之间的比率。 是0.10 <= d / T。

公开(公告)号：KR1020140038871A

公开(公告)日：2014-03-31

申请号：KR1020130081736

申请日：2013-07-11

Applicant: 삼성전기주식회사

Inventor： 안영규 ,  김두영 ,  박민철 ,  이병화 ,  박상수

IPC: H01G4/12 ,  H01G4/30 ,  H01G2/06

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/232 ,  H05K1/0231 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present invention provides a multi-layered ceramic capacitor including: a ceramic body in which a plurality of dielectric layers are layered in a width direction; first and second internal electrodes alternately disposed between the dielectric layers; first and second lead units including at least one space unit and extendedly formed to be exposed through a bottom surface of the ceramic body, while being separated from each other at the first internal electrode in a longitudinal direction; a third lead unit disposed between the first and second lead units and extendedly formed to be exposed through the bottom surface of the ceramic body at the second internal electrode; first and second external electrodes formed to be separate from each other on the bottom surface of the ceramic body and electrically connected to the first and second external electrodes, respectively; and a third external electrode formed on the bottom surface of the ceramic body between the first and second external electrodes and electrically connected to the third lead unit.

Abstract translation: 本发明提供一种多层陶瓷电容器，其包括：多个电介质层在宽度方向上层叠的陶瓷体; 交替地设置在电介质层之间的第一和第二内部电极; 第一和第二引导单元，包括至少一个空间单元，并且在第一内部电极沿纵向方向彼此分离地延伸形成为暴露于陶瓷体的底表面; 第三引线单元，设置在所述第一引线单元和所述第二引线单元之间并且被延伸地形成为在所述第二内部电极处暴露于所述陶瓷体的底表面; 第一外部电极和第二外部电极，分别形成为彼此分离，并分别电连接到第一和第二外部电极; 以及第三外部电极，其形成在所述第一外部电极和所述第二外部电极之间的所述陶瓷体的底面上并电连接到所述第三引线单元。

公开(公告)号：KR1020130135015A

公开(公告)日：2013-12-10

申请号：KR1020120126534

申请日：2012-11-09

Applicant: 삼성전기주식회사

Inventor： 안영규 ,  박민철 ,  김두영 ,  박상수

IPC: H01G4/12 ,  H01G4/30 ,  H05K1/18

CPC classification number: H01G4/30 ,  B65B9/04 ,  B65B15/04 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H05K1/181 ,  H05K2201/10015

Abstract: A laminated chip electronic component according to an embodiment of the present invention includes: a ceramic body which includes internal electrodes and dielectric layers; first and second external electrodes which are formed to cover both end parts of the longitudinal direction of the ceramic body; an active layer which forms a capacity by being arranged so that the internal electrodes face with each other across the dielectric layer; upper and lower cover layers which are formed in the upper or lower parts of the thickness direction of the active layer and in which the lower part of the thickness direction is thicker than the upper part of the thickness direction; and an additional electrode layer which is arranged regardless of capacity formation in the lower cover layer. When regulating: 1/2 of the total thickness of the ceramic body to be A; the thickness of the lower cover layer to be B; 1/2 of the total thickness of the active layer to be C; and the thickness of the upper cover layer to be D, the D which is the thickness of the upper cover layer satisfies the range of D >= 4 μm and (B+C)/A which is a ratio at which the central part of the active layer deviates from the central part of the ceramic body is able to satisfy the range of 1.069

Abstract translation: 根据本发明实施例的层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 第一和第二外部电极，其形成为覆盖陶瓷体的纵向的两个端部; 通过布置成使得内部电极在电介质层上彼此面对而形成容量的有源层; 形成在有源层的厚度方向的上部或下部的厚度方向的厚度方向的上部和下部覆盖层比厚度方向的上部厚; 以及附加的电极层，其布置成与下覆盖层中的容量形成无关。 调节时：陶瓷体总厚度的1/2为A; 下覆盖层的厚度为B; 活性层总厚度的1/2为C; 并且上覆盖层的厚度为D，作为上覆盖层的厚度的D满足D> =4μm的范围和（B + C）/ A，（B + C）/ A 偏离陶瓷体的中心部分的有源层能够满足1.069 <=（B + C）/ A <= 1.763的范围。

公开(公告)号：KR1020130135014A

公开(公告)日：2013-12-10

申请号：KR1020120126533

申请日：2012-11-09

Applicant: 삼성전기주식회사

Inventor： 안영규 ,  박상수 ,  박민철 ,  정세화

IPC: H01G4/12 ,  H01G4/30 ,  H05K1/18

CPC classification number: H01G4/005 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: A laminated chip electronic component according to an embodiment of the present invention includes: a ceramic body which includes internal electrodes and dielectric layers; external electrodes which are formed to cover both end parts of the longitudinal direction of the ceramic body; an active layer which forms a capacity by being arranged so that the internal electrodes face with each other across the dielectric layer; and upper and lower cover layers which are formed in the upper or lower parts of the thickness direction of the active layer and in which the lower part of the thickness direction is thicker than the upper part of the thickness direction. When regulating: 1/2 of the total thickness of the ceramic body to be A; the thickness of the lower cover layer to be B; 1/2 of the total thickness of the active layer to be C; and the thickness of the upper cover layer to be D, the D which is the thickness of the upper cover layer satisfies the range of D >= 4 μm and (B+C)/A which is a ratio at which the central part of the active layer deviates from the central part of the ceramic body is able to satisfy the range of 1.063

Abstract translation: 根据本发明实施例的层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为覆盖陶瓷体的长度方向的两端部的外部电极; 通过布置成使得内部电极在电介质层上彼此面对而形成容量的有源层; 以及形成在有源层的厚度方向的上部或下部中的厚度方向的厚度方向的厚度方向的厚度方向的上部和下部的覆盖层。 调节时：陶瓷体总厚度的1/2为A; 下覆盖层的厚度为B; 活性层总厚度的1/2为C; 并且上覆盖层的厚度为D，作为上覆盖层的厚度的D满足D> =4μm的范围和（B + C）/ A，（B + C）/ A 偏离陶瓷体的中心部分的有源层能够满足1.063 <=（B + C）/ A <= 1.745的范围。

公开(公告)号：KR1020120122380A

公开(公告)日：2012-11-07

申请号：KR1020110040484

申请日：2011-04-29

Applicant: 삼성전기주식회사

Inventor： 안영규 ,  박상수 ,  이병화 ,  박동석 ,  박민철 ,  김수진

IPC: H01G4/005 ,  H01G4/30

Abstract: PURPOSE: A stacked chip capacitor is provided to be used as a component for various electronic devices by being easily mounted on a circuit board. CONSTITUTION: A first inner electrode(121) and a second inner electrode(122) are faced to each other. A part without capacity is overlapped in the staked direction of the first and second inner electrode. A first part without capacity is formed in the first inner electrode. A second part without capacity is formed in the second inner electrode. The part without capacity has not a conductive pattern of an inner electrode(120).

Abstract translation: 目的：通过容易地安装在电路板上，提供堆叠式片状电容器作为各种电子器件的组件。 构成：第一内电极（121）和第二内电极（122）彼此面对。 无容量的部分在第一和第二内部电极的折叠方向上重叠。 在第一内部电极中形成无容量的第一部分。 在第二内部电极中形成第二部分无能力。 无电容部分不具有内电极（120）的导电图案。

公开(公告)号：KR1020110139993A

公开(公告)日：2011-12-30

申请号：KR1020100060148

申请日：2010-06-24

Applicant: 삼성전기주식회사

Inventor： 안영규 ,  박동석 ,  박상수 ,  박민철 ,  이병화

IPC: H01G4/12 ,  H01G4/30

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/12

Abstract: PURPOSE: A multi layered ceramic capacitor is provided to change the number of current flowing paths according to the number of an inner electrode, thereby adjusting ESR. CONSTITUTION: A multi layered capacitor(10) comprises a capacitor body which is made of a plurality of dielectric layers. First and second inner electrode groups(200,300) are formed on each dielectric layer. The first and second inner electrode groups face each other. Each dielectric layer is placed between the first and second inner electrode groups. The first and second inner electrode groups are connected to first and second external electrodes(20,30) which are formed on both sections of the capacitor body. The first and second external electrodes dip both sides of the capacitor body in a metal paste. The multi layered capacitor comprises a device on which dielectric layers are laminated, a first external electrode formed on the device, and a second external electrode which is electrically insulated from a first electrode.

Abstract translation: 目的：提供一种多层陶瓷电容器，以根据内电极的数量改变电流流动路径的数量，从而调节ESR。 构成：多层电容器（10）包括由多个电介质层制成的电容器主体。 第一和第二内部电极组（200,300）形成在每个电介质层上。 第一和第二内部电极组彼此面对。 每个电介质层被放置在第一和第二内部电极组之间。 第一和第二内部电极组连接到形成在电容器本体的两个部分上的第一和第二外部电极（20,30）。 第一和第二外部电极将电容器主体的两侧浸入金属糊料中。 多层电容器包括层叠电介质层的器件，形成在器件上的第一外部电极和与第一电极电绝缘的第二外部电极。

公开(公告)号：KR100593889B1

公开(公告)日：2006-06-28

申请号：KR1020030096397

申请日：2003-12-24

Applicant: 삼성전기주식회사

Inventor： 탁현준 ,  안영규 ,  채정훈

IPC: H01G4/30

Abstract: 본 발명은 적층 세라믹콘덴서에 관한 것으로, 유전체로 이루어진 세라믹시트가 다층으로 적층된 직육면체상의 세라믹기체; 상기 세라믹시트의 표면에 형성되는 내부전극; 상기 내부전극의 일단과 전기적으로 연결되도록 상기 세라믹기체의 양단부에 형성되는 외부전극;및 상기 내부전극와 중첩되지 않도록 상기 내부전극이 형성되지 않은 나머지 영역인 사이드마진부에 상기 내부전극의 길이방향으로 평행하게 독립적으로 형성되는 적어도 하나이상의 보강패턴;을 포함하여 구성된다.
본 발명에 의하면, 열충격신뢰성시험시 세라믹기체의 외부전극으로부터 내부전극으로의 진행되는 크랙의 진로를 저지하여 전자부품의 전기적인 특성이 저하되는 것을 방지하고, 제품신뢰성을 높일 수 있다.
적층세라믹 콘덴서, 보강패턴, 세라믹기체, 세라믹시트, 내부전극, 외부전극

Abstract translation: 本发明中，由介电陶瓷片的堆叠在陶瓷体与多层陶瓷电容器的长方体多层; 内部电极形成在陶瓷片的表面上; 被连接到一个端部，并电形成在所述陶瓷体的两端的内部电极的外部电极;平行于和侧边缘部分，并且其中所述内部电极不形成为不重叠的内jeongeukwa在内部电极的纵向方向上的剩余区域 并且至少一个彼此独立形成的加强图案。