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公开(公告)号：KR1020130135014A
公开(公告)日：2013-12-10
申请号：KR1020120126533
申请日：2012-11-09
Applicant: 삼성전기주식회사
CPC classification number: H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
Abstract: A laminated chip electronic component according to an embodiment of the present invention includes: a ceramic body which includes internal electrodes and dielectric layers; external electrodes which are formed to cover both end parts of the longitudinal direction of the ceramic body; an active layer which forms a capacity by being arranged so that the internal electrodes face with each other across the dielectric layer; and upper and lower cover layers which are formed in the upper or lower parts of the thickness direction of the active layer and in which the lower part of the thickness direction is thicker than the upper part of the thickness direction. When regulating: 1/2 of the total thickness of the ceramic body to be A; the thickness of the lower cover layer to be B; 1/2 of the total thickness of the active layer to be C; and the thickness of the upper cover layer to be D, the D which is the thickness of the upper cover layer satisfies the range of D >= 4 μm and (B+C)/A which is a ratio at which the central part of the active layer deviates from the central part of the ceramic body is able to satisfy the range of 1.063
Abstract translation: 根据本发明实施例的层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为覆盖陶瓷体的长度方向的两端部的外部电极; 通过布置成使得内部电极在电介质层上彼此面对而形成容量的有源层; 以及形成在有源层的厚度方向的上部或下部中的厚度方向的厚度方向的厚度方向的厚度方向的上部和下部的覆盖层。 调节时：陶瓷体总厚度的1/2为A; 下覆盖层的厚度为B; 活性层总厚度的1/2为C; 并且上覆盖层的厚度为D，作为上覆盖层的厚度的D满足D> =4μm的范围和（B + C）/ A，（B + C）/ A 偏离陶瓷体的中心部分的有源层能够满足1.063 <=（B + C）/ A <= 1.745的范围。
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Patent Agency Ranking
公开(公告)号：KR101616596B1
公开(公告)日：2016-04-28
申请号：KR1020120126533
申请日：2012-11-09
Applicant: 삼성전기주식회사
CPC classification number: H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
Abstract: 본발명의일 실시예에따른적층칩 전자부품은내부전극과유전체층을포함하는세라믹바디; 상기세라믹바디의길이방향의양 단부를덮도록형성되는외부전극; 상기유전체층을사이에두고상기내부전극이대향하여배치되어용량이형성되는엑티브층; 및상기엑티브층의두께방향상부또는하부에형성되며, 두께방향하부가두께방향상부보다더 큰두께를가지는상부및 하부커버층;을포함하며, 상기세라믹바디의전체두께의 1/2을 A로, 상기하부커버층의두께를 B로, 상기엑티브층의전체두께의 1/2을 C로, 상기상부커버층의두께를 D로규정할때, 상기상부커버층의두께, D는 D≥4㎛의범위를만족하고, 상기엑티브층의중심부가상기세라믹바디의중심부로부터벗어난비율, (B+C)/A는 1.063≤(B+C)/A≤1.745의범위를만족할수 있다.
Abstract translation: 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。
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公开(公告)号：KR101309479B1
公开(公告)日：2013-09-23
申请号：KR1020120089522
申请日：2012-08-16
Applicant: 삼성전기주식회사
CPC classification number: H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
Abstract: PURPOSE: A laminated chip electronic component, a board for mounting the same and a packing unit thereof are provided to increase the thickness of a lower cover layer, thereby remarkably reducing acoustic noise. CONSTITUTION: A ceramic body includes an inner electrode (20) and a dielectric layer (50). Outer electrodes (42,44) are formed in order to cover the both end parts in a longitudinal direction of the ceramic body. An active layer is arranged in order to face the inner electrode places across the dielectric layer. A top cover layer and a lower cover layer (53,55) are formed at the upper part and lower part of a thickness direction of the active layer. And the thickness of the lower part of the thickness direction is thicker than that of the upper part. The half of the total thickness of the ceramic body is described as A. The thickness of the lower cover layer is described as B. The half of the total thickness of the active layer is described as C. The thickness of the top cover layer is described as D. The D, which is the thickness of the top cover layer, satisfies a range of D>=4um. (B+C)/A is a ratio in which the central part of the active layer deviates from the central part of the ceramic body and satisfies a range of 1.063
Abstract translation: 目的：提供层叠芯片电子部件，其安装基板及其包装单元，以增加下覆盖层的厚度，从而显着降低声学噪声。 构成：陶瓷体包括内电极（20）和电介质层（50）。 形成外电极（42,44），以便在陶瓷体的长度方向上覆盖两端部。 布置有源层以便穿过电介质层面对内部电极。 在有源层的厚度方向的上部和下部形成顶盖层和下覆盖层（53,55）。 并且厚度方向的下部的厚度比上部的厚度厚。 陶瓷体的总厚度的一半被描述为A.下覆盖层的厚度描述为B.活性层的总厚度的一半被描述为C.顶盖层的厚度为 描述为D.D，其顶层的厚度满足D> = 4um的范围。 （B + C）/ A是活性层的中心部分偏离陶瓷体的中心部分的比例，满足1.063 <=（B + C）/ A <= 1.745的范围。
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公开(公告)号：KR1020140120111A
公开(公告)日：2014-10-13
申请号：KR1020130035794
申请日：2013-04-02
Applicant: 삼성전기주식회사
Inventor： 정세화
Abstract: 본 발명은, 복수의 유전체층이 적층된 세라믹 본체; 상기 세라믹 본체 내에서 상기 유전체층을 사이에 두고 상기 세라믹 본체의 양 단면을 통해 번갈아 노출되도록 배치된 복수의 제1 및 제2 내부 전극; 및 상기 세라믹 본체의 양 단면에 각각 형성되며, 상기 제1 및 제2 내부 전극과 각각 전기적으로 연결된 제1 및 제2 외부 전극; 을 포함하며, 상기 제2 내부 전극은, 상기 세라믹 본체의 일 단면을 통해 노출된 리드부와 상기 제1 내부 전극과 오버랩되는 용량부를 포함하며, 상기 용량부의 길이 및 폭이 상기 제1 내부 전극의 길이 및 폭 보다 각각 작으며, 상기 제2 내부 전극의 리드부와 용량부를 연결하는 연결부가 병목 형태로 형성된 적층 세라믹 커패시터를 제공한다.
Abstract translation: 本发明提供一种多层陶瓷电容器，其包括层叠有多个电介质层的陶瓷体，多个第一和第二内部电极，其被布置成通过插入电介质来交替地暴露于陶瓷体的两端侧 陶瓷体中的层，以及形成在陶瓷体的两端侧并分别电连接到第一和第二内部电极的第一和第二外部电极。 第二内部电极包括通过陶瓷体的一端侧暴露的引线部和与第一内部电极重叠的电容部。 容量部分的长度和宽度分别小于第一内部电极的长度和宽度。 连接第二内部电极的电容部和引线部的连接部形成为瓶颈形状。
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公开(公告)号：KR1020140028092A
公开(公告)日：2014-03-07
申请号：KR1020140008460
申请日：2014-01-23
Applicant: 삼성전기주식회사
CPC classification number: H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
Abstract: A laminated chip electronic component according to one embodiment of the present invention comprises: a ceramic body including internal electrodes and dielectric layers; an external electrode formed to cover both end portions of the ceramic body in a length direction of the ceramic body; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction of the active layer, the lower cover layer having a thickness greater than that of the upper cover layer, wherein when a half of a thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, a half of a thickness of the active layer is defined as C, and a thickness of the upper cover layer is defined as D, the thickness D of the upper cover layer satisfies a range of D>=4μm and a ratio (B+C)/A by which a central portion of the active layer deviates from a central portion of the ceramic body satisfies a range of 1.063
Abstract translation: 根据本发明的一个实施例的层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 外部电极，其形成为在陶瓷体的长度方向上覆盖陶瓷体的两端部; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 在有源层的厚度方向上形成在有源层的上部和下部上的上覆盖层和下覆盖层，下覆盖层的厚度大于上覆盖层的厚度，其中当陶瓷的厚度的一半时， 主体被定义为A，下覆盖层的厚度定义为B，有源层的厚度的一半被定义为C，并且上覆盖层的厚度被定义为D，厚度D 上覆盖层满足D> =4μm的范围和有源层的中心部分偏离陶瓷体的中心部分的比例（B + C）/ A满足1.063 <=（B + C ）/ A <= 1.745。
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