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公开(公告)号：KR100837282B1
公开(公告)日：2008-06-12
申请号：KR1020070058414
申请日：2007-06-14
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/26 , G11C2216/14 , G11C16/0483 , G11C16/3459
Abstract: A non-volatile memory device, a memory system having the same, and a programming method and a reading method thereof are provided to improve reliability of read operation even though a threshold voltage is changed. A memory cell array(100) includes a main region having memory cells arranged on regions where a plurality of word lines and a plurality of bit lines are crossed, and an index region having memory cells arranged on regions where the plurality of word lines and a plurality of index bit lines are crossing. The main region has memory cells where user data bits are stored. The index region has an index cell storing index bits to inform the variation of a threshold voltage and threshold voltage information cells storing data bits for an initial threshold voltage of the index cell. A row decoder(200) selects one of the plurality of word lines by receiving an address. A word line voltage generator(300) provides a word line voltage to the selected word line in response to a step code. A page buffer(400) stores the user data bits to be programmed in the main region or stores data bits sensed through the plurality of bit lines from the main region, and stores the index bits to be programmed in the index region and data bits for the initial threshold voltage value or the index bits sensed through the plurality of index bit lines from the index region and data bits for the initial threshold voltage value temporarily. A control logic(500) controls the word line voltage generator and the page buffer, and generates the step code applied to the word line voltage generator.
Abstract translation: 提供了一种非易失性存储器件，具有其的存储器系统及其编程方法和读取方法，以提高读取操作的可靠性，即使阈值电压改变。 一种存储单元阵列（100）包括具有布置在多个字线和多个位线交叉的区域上的存储单元的主区域和具有存储单元的索引区域，该区域布置在多个字线和 多个索引位线正在交叉。 主区域具有存储用户数据位的存储单元。 索引区域具有存储索引位的索引单元，用于通知阈值电压的变化，以及存储针对索引单元的初始阈值电压的数据位的阈值电压信息单元。 行解码器（200）通过接收地址来选择多个字线中的一个。 字线电压发生器（300）响应于步进代码向所选择的字线提供字线电压。 页面缓冲器（400）将要编程的用户数据位存储在主区域中，或者存储从主区域通过多个位线检测的数据位，并将要编程的索引位存储在索引区域中，数据位用于 初始阈值电压值或从索引区域检测到的多个索引位线的索引位和临时初始阈值电压值的数据位。 控制逻辑（500）控制字线电压发生器和页缓冲器，并产生施加到字线电压发生器的步码。
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公开(公告)号：KR1020080052288A
公开(公告)日：2008-06-11
申请号：KR1020070080179
申请日：2007-08-09
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1006 , G11C11/5621 , G11C16/06 , G11C29/38
Abstract: A multi-level cell memory device using concatenated coding is provided to store more than four bits in one memory cell by increasing the number of bits stored in one memory stably. A multi-level cell memory device includes an MLC(Multi Level Cell) memory cell(240), an outer encoder(210), an inner encoder(220) and a signal mapping module(230). The outer encoder generates outer encoded bit stream by encoding the data through first encoding method. The inner encoder generates inner encoded bit stream by encoding the outer encoded bit stream through second encoding method. The signal mapping module writes the data in the MLC memory cell by applying a program pulse according to the inner encoded bit stream to the MLC memory cell.
Abstract translation: 提供了使用级联编码的多级单元存储器件，用于通过增加存储在一个存储器中的比特数来稳定地存储在一个存储单元中的四位以上。 多级单元存储器件包括MLC（多级单元）存储单元（240），外编码器（210），内编码器（220）和信号映射模块（230）。 外部编码器通过第一编码方法对数据进行编码来生成外部编码比特流。 内部编码器通过第二编码方法对外部编码比特流进行编码来生成内部编码比特流。 信号映射模块通过根据内部编码比特流将编程脉冲施加到MLC存储器单元来将数据写入MLC存储器单元。
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公开(公告)号：KR100822030B1
公开(公告)日：2008-04-15
申请号：KR1020060134049
申请日：2006-12-26
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/0483
Abstract: A multi-level cell memory device using high rate code is provided to minimize overhead of encoding and decoding as increasing the number of bits stored in one multi-level cell, by writing data in the multi-level cell memory through encoding of high code rate. A multi-level cell memory device storing data includes a groups of m-bit MLC(Multi-Level Cell) memory cells(261,262,263,264) where a and m are an integer above 2, an encoder(210) and a signal mapping part(220). The encoder generates encoded bit stream by encoding k bit data with code rate of k/n. The signal mapping part writes the encoded bit stream in the groups of m-bit MLC memory cells by applying a pulse according to the encoded bit stream to the group of m-bit MLC memory cells.
Abstract translation: 提供了一种使用高速码的多级信元存储装置，通过将多码单元存储器中的数据通过编码高码率进行写入，从而最小化编码和解码的开销，因为存储在一个多电平单元中的位数增加 。 存储数据的多级单元存储器件包括一组m位MLC（多级单元）存储单元（261,262,263,264），其中a和m是大于2的整数，编码器（210）和信号映射部分（220 ）。 编码器通过以k / n的码率对k位数据进行编码来生成编码比特流。 信号映射部分通过将编码的比特流应用到m比特MLC存储器单元组来将编码的比特流写入m比特MLC存储器单元的组中。
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公开(公告)号：KR100805840B1
公开(公告)日：2008-02-21
申请号：KR1020060084270
申请日：2006-09-01
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3454 , G11C11/5628 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
Abstract: A flash memory device using a program data cache and a program method thereof are provided to remove coupling influence according to program operation of adjacent cells by selecting reprogrammed cells using the cache after first program operation performed with a low program verify voltage. According to a program method of a flash memory device, plural data to be programmed are loaded on a program cache(S10). A part of the plural data are written into selected memory cells according to a first verify voltage(S20). Rewrite operation for the selected memory cells is judged by referring to the plural data loaded on the program cache. A part of the plural data are rewritten into the selected memory cells according to a second verify voltage lower than the first verify voltage, according to the judgment result(S60).
Abstract translation: 提供使用程序数据高速缓冲存储器及其编程方法的闪速存储器件，以通过使用低程序验证电压进行的第一程序操作之后通过使用高速缓存选择重新编程的单元，来消除根据相邻单元的编程操作的耦合影响。 根据闪存装置的编程方法，将要编程的多个数据加载到程序高速缓存上（S10）。 根据第一验证电压将多个数据的一部分写入选择的存储单元（S20）。 通过参考加载在程序缓存上的多个数据来判断所选存储单元的重写操作。 根据判断结果，将多个数据的一部分根据低于第一验证电压的第二验证电压重写到选择的存储单元中（S60）。
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公开(公告)号：KR1020070029299A
公开(公告)日：2007-03-14
申请号：KR1020050083921
申请日：2005-09-09
Applicant: 삼성전자주식회사
Abstract: A nonvolatile semiconductor memory device having a dummy cell arranged in a cell string is provided to have the same operation characteristic for all memory cells, by making the conditions of the adjacent memory cells equal. In a nonvolatile semiconductor memory device, a cell string(110) is electrically erasable and programmable and includes a number of nonvolatile memory cells, a selection gate transistor serially connected to the memory cells, and a dummy cell inserted between the memory cell at one end and the selection gate transistor. The dummy cell is not used for storing data. A normal word line driver(310) selectively enables normal word lines gating the memory cells. A dummy word line driver(330,350) enables a dummy word line gating the dummy cell. The dummy word line driver is specified by a row address specifying the normal word line driver.
Abstract translation: 通过使相邻的存储单元的条件相等，具有布置在单元串中的虚设单元的非易失性半导体存储器件被设置为具有与所有存储单元相同的操作特性。 在非易失性半导体存储器件中，单元串（110）是电可擦除和可编程的，并且包括多个非易失性存储单元，串联连接到存储单元的选择栅极晶体管，以及一端插入在存储单元之间的虚拟单元 和选择栅极晶体管。 虚拟单元不用于存储数据。 通常的字线驱动器（310）选择性地启用门控存储器单元的正常字线。 虚拟字线驱动器（330,350）使得能够选通虚拟单元的虚拟字线。 虚拟字线驱动程序由指定正常字线驱动程序的行地址指定。
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Patent Agency Ranking
公开(公告)号：KR100683858B1
公开(公告)日：2007-02-15
申请号：KR1020060003587
申请日：2006-01-12
Applicant: 삼성전자주식회사
Abstract: A program method of a flash memory, capable of compensating read margin reduction due to hot temperature stress(HTS) is provided to secure a sufficient read margin between adjacent states, in spite of threshold voltage increase due to electric field coupling/F-poly coupling and threshold voltage decrease due to HTS. According to a program method of a flash memory device comprising a plurality of memory cells to store multi-bit data indicating one of a plurality of states, memory cells selected to have one of the states are programmed with multi-bit data. The programmed memory cells belonging to a specific region of a threshold voltage distribution corresponding to each of at least two states are detected. The specific region of each of the two states is selected by one of a first verify voltage and a read voltage and a second verify voltage, where the second verify voltage is higher than the first verify voltage and the read voltage is lower than the first verify voltage. The detected memory cells of the two states are simultaneously programmed to have a threshold voltage equal to or higher than the second verify voltage corresponding to each of the two states.
Abstract translation: 尽管阈值电压由于电场耦合/ F-poly耦合而增加，但为了确保相邻状态之间足够的读取裕度，提供了能够补偿由热温度应力（HTS）引起的读取裕量减少的闪存的编程方法 并且由于HTS导致阈值电压下降。 根据包括用于存储指示多个状态之一的多位数据的多个存储器单元的闪存器件的编程方法，被选择为具有一个状态的存储器单元被编程有多位数据。 检测属于对应于至少两个状态中的每一个状态的阈值电压分布的特定区域的已编程存储器单元。 通过第一验证电压和读取电压以及第二验证电压中的一个来选择两个状态中的每一个的特定区域，其中第二验证电压高于第一验证电压并且读取电压低于第一验证 电压。 两个状态的检测到的存储器单元被同时编程为具有等于或高于对应于两个状态中的每一个的第二验证电压的阈值电压。
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