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公开(公告)号：KR1019930008081B1
公开(公告)日：1993-08-25
申请号：KR1019910001340
申请日：1991-01-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: A single-poly EEPROM cell having two selective transistors and a sense transistor, comprises a first capacitor and a second capacitor. The first capacitor is composed of a doping region formed on a semiconductor substrate, a first tunneling insulating film formed on the doping region and a streched conductive film covered over the insulating film. The second capacitor comprises a second doping region formed on the region away from the first doping region, a second tunneling insulating film, which is made of oxide film-nitride film-oxide film, formed between the second doping region and a conductive film.
Abstract translation: 具有两个选择性晶体管和感测晶体管的单层多层EEPROM单元包括第一电容器和第二电容器。 第一电容器由形成在半导体衬底上的掺杂区域，形成在掺杂区域上的第一隧道绝缘膜和覆盖在绝缘膜上的拉伸导电膜组成。 第二电容器包括形成在远离第一掺杂区域的区域上的第二掺杂区域，形成在第二掺杂区域和导电膜之间的由氧化物膜氮化物膜氧化膜制成的第二隧道绝缘膜。
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公开(公告)号：KR1019920013709A
公开(公告)日：1992-07-29
申请号：KR1019900021387
申请日：1990-12-21
Applicant: 삼성전자주식회사
IPC: H01L29/788
Abstract: 내용 없음
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公开(公告)号：KR1019910009614B1
公开(公告)日：1991-11-23
申请号：KR1019880016327
申请日：1988-12-08
Applicant: 삼성전자주식회사
IPC: H01L27/10
Abstract: The electrically erasable and programmable read only memory device (EEPROM) for increasing the coupling ratio comprises the select transistor having a select gate (44) and the sensing transistor having control and floating gate. A floating gate is formed on the semiconductor substrate surface so that it is electrically isolated by spacer (64) formed on both side of select gate and contacted with tunnel oxide film (42). Source and drain regions are formed in the substrate by using the gate and spacer as a mask.
Abstract translation: 用于增加耦合比的电可擦除可编程只读存储器件（EEPROM）包括具有选择栅极（44）的选择晶体管和具有控制和浮置栅极的感测晶体管。 在半导体衬底表面上形成浮栅，使其通过形成在选择栅极两侧并与隧道氧化膜（42）接触的间隔物（64）电隔离。 通过使用栅极和间隔物作为掩模在衬底中形成源区和漏区。
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公开(公告)号：KR1020120061552A
公开(公告)日：2012-06-13
申请号：KR1020100122894
申请日：2010-12-03
Applicant: 삼성전자주식회사
IPC: H01L21/3105 , H01L21/336
Abstract: PURPOSE: A semiconductor device manufacturing method which includes annealing processes is provided to prevent degradation of electrical properties of a semiconductor device by effectively curing dangling bonds formed on a gate insulating film. CONSTITUTION: A gate structure(110) which includes a gate electrode and a gate insulating film is formed on a substrate. A first interlayer insulating film(120) is formed on the substrate with a hydrogen bond by covering the gate structure. Hydrogen inside the first interlayer insulating film is eliminated by performing a first annealing process under a gas atmosphere not including hydrogen. A second annealing process is performed under a gas atmosphere including hydrogen.
Abstract translation: 目的：提供包括退火处理的半导体器件制造方法，以通过有效地固化形成在栅极绝缘膜上的悬挂键来防止半导体器件的电特性的劣化。 构成：在基板上形成包括栅极电极和栅极绝缘膜的栅极结构（110）。 通过覆盖栅极结构，在具有氢键的衬底上形成第一层间绝缘膜（120）。 通过在不包含氢的气体气氛下进行第一退火处理来消除第一层间绝缘膜内的氢。 第二退火工艺在包含氢的气体气氛下进行。
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公开(公告)号：KR1020080035356A
公开(公告)日：2008-04-23
申请号：KR1020060101966
申请日：2006-10-19
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L27/11521 , H01L29/42324 , H01L21/28273 , H01L21/76838
Abstract: An NVM(non-volatile memory) device is provided to avoid malfunction of a memory cell by interposing an isolation layer between a protrusion part of a wordline and an active region. An isolation layer(113) for defining an active region(109) is formed on a semiconductor substrate(101). Patterns for floating gates(119) are formed on the active region, protruding from the isolation layer. A concave part(125) is formed on the isolation layer between the patterns for the floating gates. A wordline is formed on the patterns for the floating gates, having a protrusion part(130) filling the concave region. The process for forming the concave region can include the following steps. A molding insulation layer is formed along the upper surface and both sidewalls of the patterns for the floating gate and along the upper surface of the isolation layer. The molding insulation layer is anisotropically etched to form molding spacers on both sidewalls of the patterns for the floating gates. The isolation layer is etched by using the molding spacers as an etch mask.
Abstract translation: 提供NVM（非易失性存储器）装置，以通过在字线的突出部分和活动区域之间插入隔离层来避免存储器单元的故障。 在半导体衬底（101）上形成用于限定有源区（109）的隔离层（113）。 浮动栅极（119）的图案形成在从隔离层突出的有源区域上。 在浮动栅极的图案之间的隔离层上形成凹部（125）。 在浮动栅极的图案上形成有字线，具有填充凹入区域的突起部分（130）。 形成凹区域的方法可以包括以下步骤。 沿着浮动栅极的图案的上表面和两个侧壁以及隔离层的上表面形成成型绝缘层。 成型绝缘层被各向异性蚀刻以在浮动栅极的图案的两个侧壁上形成模制间隔物。 通过使用模制间隔物作为蚀刻掩模来蚀刻隔离层。
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Patent Agency Ranking
公开(公告)号：KR100822807B1
公开(公告)日：2008-04-18
申请号：KR1020060102571
申请日：2006-10-20
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/66833 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/7881 , H01L29/792 , H01L21/28273 , H01L21/28282
Abstract: A flash memory device and a manufacturing method thereof are provided to improve compensate impurity diffusion without increasing an overall concentration of a channel impurity layer. When an isolation layer(72) is formed, a p-type impurity of a first channel impurity layer(56) is diffused, so that a concentration of the first channel impurity layer decreases. In particular, impurity concentration of the first channel impurity layer is lowered at a boundary between the isolation layer and an active region. To compensate for the decrease in impurity, a second channel impurity(74) is implanted into the first channel impurity layer to increase the concentration of the first channel impurity layer. In particular, the second channel impurity is additionally implanted into edges(52a) of the active region.
Abstract translation: 提供闪速存储器件及其制造方法以改善补偿杂质扩散，而不增加沟道杂质层的总体浓度。 当形成隔离层（72）时，第一沟道杂质层（56）的p型杂质扩散，使得第一沟道杂质层的浓度降低。 特别地，第一沟道杂质层的杂质浓度在隔离层和有源区域之间的边界处降低。 为了补偿杂质的减少，第二沟道杂质（74）被注入到第一沟道杂质层中以增加第一沟道杂质层的浓度。 特别地，第二通道杂质另外注入到有源区的边缘（52a）中。
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公开(公告)号：KR100784868B1
公开(公告)日：2007-12-14
申请号：KR1020060021439
申请日：2006-03-07
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: 비대칭 게이트 전극 구조를 갖는 선택 트랜지스터 및 대략 'ㅗ' 형태를 나타내는 플로팅 게이트를 갖는 메모리 트랜지스터 그리고 이들의 형성 방법이 제공된다. 메모리 트랜지스터에 인접한 선택 트랜지스터의 게이트 전극부는 그 단면이 대략 'ㅗ' 형태이고, 메모리 트랜지스터 맞은 편의 선택 트랜지스터의 게이트 전극부는 그 단면이 대략 박스 형태이다. 메모리 트랜지스터의 플로팅 게이트를 'ㅗ' 형태로 형성하기 위해 메모리 트랜지스터가 형성되는 영역을 개방할 때, 선택 트랜지스터가 형성되는 영역을 폐쇄한다.
플래시 메모리, 플로팅 게이트, 커플링 비율, 로딩 효과-
公开(公告)号：KR1020070006474A
公开(公告)日：2007-01-11
申请号：KR1020050061836
申请日：2005-07-08
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/42324 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11526
Abstract: An NVM(non-volatile memory) device is provided to reduce an overlap area between adjacent floating gates by including a flat part and a pair of walls extending upward from both edges of the flat part. An isolation layer is formed in a substrate(100) to define an active region. A floating gate is disposed on the active region by interposing a tunnel insulation layer(115), including a flat part(116a) and a pair of walls extending upward from both edges of the flat part. A control gate electrode(135a) is disposed on the floating gate, covering the outer surface of the wall adjacent to the isolation layer. A blocking insulation pattern(130a) is interposed between the control gate electrode and the floating gate. An impurity doping layer is formed in the active region at both sides of the control gate electrode. A space surrounded by the flat part and the pair of walls is filled with an insulation material. A capping pattern(125b) is included in the space wherein the insulation material filled in the space includes the capping pattern.
Abstract translation: 提供NVM（非易失性存储器）装置，通过包括从平坦部分的两个边缘向上延伸的平坦部分和一对壁来减小相邻浮动栅极之间的重叠区域。 在衬底（100）中形成隔离层以限定有源区。 通过插入包括平坦部分（116a）和从平坦部分的两个边缘向上延伸的一对壁的隧道绝缘层（115），将浮动栅极设置在有源区域上。 控制栅电极（135a）设置在浮动栅极上，覆盖与隔离层相邻的壁的外表面。 阻挡绝缘图案（130a）插入在控制栅电极和浮栅之间。 在控制栅电极两侧的有源区中形成杂质掺杂层。 由平坦部分和一对墙壁围绕的空间填充有绝缘材料。 在空间中包括封盖图案（125b），其中填充在空间中的绝缘材料包括封盖图案。
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公开(公告)号：KR100655435B1
公开(公告)日：2006-12-08
申请号：KR1020050071477
申请日：2005-08-04
Applicant: 삼성전자주식회사
IPC: H01L21/8247
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