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公开(公告)号：KR100474850B1
公开(公告)日：2005-03-11
申请号：KR1020020071042
申请日：2002-11-15
Applicant: 삼성전자주식회사 , 대한민국(서울대학교 총장)
IPC: H01L27/115
CPC classification number: H01L29/7926 , G11C11/5628 , H01L21/28282 , H01L29/66833 , H01L29/785 , H01L29/7923
Abstract: 수직 채널을 가지는 SONOS 메모리 및 그 제조방법이 개시된다. 개시된 수직 채널을 가지는 SONOS 메모리는, 기판과, 기판 상에 적층되는 제1절연층과, 제1절연층의 상면에 소정 형태로 패터닝되며 소정 간격 이격된 소스 및 드레인 전극을 포함하는 반도체층과, 반도체층의 상면에서 소스 및 드레인 전극 사이에 위치하는 제2절연층과, 반도체층의 소스 및 드레인 전극 사이의 측면과 제2절연층의 측면 및 상면에 증착되며 전자 이동 채널과 전자 저장막을 포함하는 메모리층 및, 메모리층의 표면에 증착되어 메모리층의 전자 이동을 조절하는 게이트 전극을 구비한다. 채널폭을 감소시켜 고집적의 대용량 메모리를 구현할 수 있다.
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公开(公告)号：KR100442815B1
公开(公告)日：2004-10-14
申请号：KR1019980015989
申请日：1998-05-04
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A single electron transistor and a fabricating method thereof are provided to improve reproducibility and homogeneity of a size of an island by using porous silicon as the island of the single electron transistor. CONSTITUTION: A porous silicon layer(40) including apertures having diameters less than 5nm is formed on a substrate(10). A source(20) and a drain(30) are formed on both sides of the porous silicon layer by using a metal. An insulating layer(50) is formed on the porous silicon layer by using an oxide. A gate(60) is formed on the insulating layer. The substrate is formed with an SOI substrate. A thickness of the porous layer is less than 10nm.
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公开(公告)号：KR100446632B1
公开(公告)日：2004-09-04
申请号：KR1020020062482
申请日：2002-10-14
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , B82Y10/00
CPC classification number: H01L21/28194 , B82Y10/00 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7885 , H01L29/7887 , H01L29/7888
Abstract: A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) memory is provided. The provided SONSNOS memory includes first and second insulating layers (111a,111b) stacked on the channel of the substrate, first and second dielectric layers (113a,113b) formed on the first insulating layer (111a) and under the second insulating layer (111b), respectively, a group IV semiconductor layer (115), silicon quantum dots, or metal quantum dots interposed between the first and second dielectric layers (113a,113b). The provided SONSNOS memory improves a programming rate and the capacity of the memory.
Abstract translation: 提供非易失性硅/氧化物/氮化物/硅/氮化物/氧化物/硅（SONSNOS）存储器。 所提供的SONSNOS存储器包括堆叠在衬底的沟道上的第一和第二绝缘层（111a，111b），在第一绝缘层（111a）上和第二绝缘层（111b）下方形成的第一和第二介电层（113a，113b） ），第IV族半导体层（115），硅量子点或介于第一和第二介电层（113a，113b）之间的金属量子点。 所提供的SONSNOS存储器提高了编程速率和存储器容量。 ＆lt;图像＆GT; ＆lt;图像＆GT;
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公开(公告)号：KR1020040026264A
公开(公告)日：2004-03-31
申请号：KR1020020057644
申请日：2002-09-23
Applicant: 삼성전자주식회사
Inventor： 김정우
IPC: G11B19/02
Abstract: PURPOSE: A system and a method for controlling volume of a music file are provided to automatically control a volume level of the music file constantly when a plurality of music files are continuously played. CONSTITUTION: A volume information detector(201) detects the volume information added to an area of the compressed music file if playback of the compressed music file is requested. A decoder(201) decodes the compressed music file in order to recover the compressed music file to an original state. A volume controller(203) controls the volume of an audio signal output from the decoder based on the detected volume information. If the compressed music files is a plural number, the volume information detector detects the volume information of each compressed music file.
Abstract translation: 目的：提供一种用于控制音乐文件音量的系统和方法，用于当连续播放多个音乐文件时，不断地自动控制音乐文件的音量。 构成：如果请求了压缩音乐文件的回放，则音量信息检测器（201）检测添加到压缩音乐文件区域的音量信息。 解码器（201）对压缩的音乐文件进行解码，以将压缩的音乐文件恢复到原始状态。 音量控制器（203）基于检测到的音量信息来控制从解码器输出的音频信号的音量。 如果压缩音乐文件是复数，则音量信息检测器检测每个压缩音乐文件的音量信息。
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45.发明公开양자 도트를 이용한 비휘발성 단일 전자 트랜지스터 메모리와 그 제조방법 및 양자 도트를 이용한 단일 전자 트랜지스터와 그 제조방법 失效非挥发性单电子晶体管存储器使用量子点及其方法，以及使用量子点的单电子晶体管及其方法
公开(公告)号：KR1020000055239A
公开(公告)日：2000-09-05
申请号：KR1019990003754
申请日：1999-02-04
Applicant: 삼성전자주식회사
IPC: H01L27/115 , B82Y10/00
Abstract: PURPOSE: A non volatile single electron transistor memory is provided to secure a repeatability and a uniformity of an island by using a quantum dot for precisely controlling the size of the island to a unit of nanometer. CONSTITUTION: A non volatile single electron transistor memory comprises a silicon substrate(100), quantum dots(110) of a predetermined size, a source(120) and a drain(130), and a side gate. A SiO2 oxidation layer(100b) is formed on the silicon substrate. The quantum dots of a predetermined size are separated a predetermined interval from each other on the SiO2 oxidation layer. The source and drain are formed by evaporating a metal on the SiO2 oxidation layer including the quantum dots, having a predetermined number of the quantum dots used as an island, between the source and the drain. The side gate is formed on the SiO2 oxidation layer at a side surface of the source and drain, having a predetermined interval from the source and drain.
Abstract translation: 目的：提供非挥发性单电子晶体管存储器，以通过使用用于将岛的尺寸精确地控制到纳米单位的量子点来确保岛的重复性和均匀性。 构成：非易失性单电子晶体管存储器包括硅衬底（100），预定尺寸的量子点（110），源极（120）和漏极（130）以及侧栅极。 在硅衬底上形成SiO 2氧化层（100b）。 预定尺寸的量子点在SiO 2氧化层上彼此隔开预定的间隔。 源极和漏极通过在源极和漏极之间蒸发包括量子点的SiO 2氧化层上的金属形成，该量子点具有预定数量的用作岛的量子点。 在源极和漏极的侧表面上的SiO 2氧化层上形成侧栅，源极和漏极具有预定的间隔。
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Patent Agency Ranking
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公开(公告)号：KR102237820B1
公开(公告)日：2021-04-08
申请号：KR1020140057952
申请日：2014-05-14
Applicant: 삼성전자주식회사
IPC: H01L27/146
Abstract: 개시된수평형포토다이오드는기판; 상기기판상에형성된절연마스크층; 상기절연마스크층의일면에접촉하며, 상기일면과나란한방향을따라순차배치된제1형반도체층, 활성층, 제2형반도체층;을포함한다. 상기절연마스크층은관통홀이구비되어, 상기제1형반도체층, 활성층, 제2형반도체층이상기관통홀로부터측면과성장법에의해형성된다.
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