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公开(公告)号：KR1020110093373A
公开(公告)日：2011-08-18
申请号：KR1020100013390
申请日：2010-02-12
Applicant: 삼성전자주식회사
CPC classification number: G06F13/1673 , Y02D10/14
Abstract: PURPOSE: A memory controller and computing device in which the memory controller is mounted are provided to improve a memory access bandwidth. CONSTITUTION: A memory controller(30) access a memory(90) with an arranged word unit and stores the memory in a data buffer. The memory controller extracts and outputs a requested data by responding to an unarranged memory access request of a processor. The memory controller includes a memory access unit(70) which access the memory with the arranged word unit and the tagged buffer(50).
Abstract translation: 目的：提供安装存储器控制器的存储器控制器和计算装置，以改善存储器存取带宽。 构成：存储器控制器（30）用排列的字单元访问存储器（90）并将该存储器存储在数据缓冲器中。 存储器控制器通过响应处理器的未经规定的存储器访问请求来提取并输出所请求的数据。 存储器控制器包括存储器访问单元（70），该存储器访问单元（70）利用排列的字单元和标记的缓冲器（50）访问存储器。
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42.发明公开
公开(公告)号：KR1020100094214A
公开(公告)日：2010-08-26
申请号：KR1020090013532
申请日：2009-02-18
Applicant: 삼성전자주식회사
CPC classification number: G06F15/82 , G06F9/30072 , G06F9/3853 , G06F9/06 , G06F9/30192 , G06F9/30196 , G06F17/606 , G06F17/608
Abstract: PURPOSE: An apparatus and a method for generating a VLIW(Very Long Instruction Word) instruction, and a VLIW processor and a method for processing the VLIW instruction are provided to configure and process the VLIW instruction by generating the instruction bundles through a VLIW instruction. CONSTITUTION: An instruction fetching unit(410) fetches an instruction bundle, and the instruction bundle is plural instructions performed in parallel and comprises the value showing the conditional execution by bundle unit. A decoder(420) decodes the instruction bundle. A command execution unit(430) performs instructions included in the instruction bundle according to value showing the conditional execution in parallel. The value showing the conditional execution is an index of a predicate register file.
Abstract translation: 目的：提供用于生成VLIW（超长指令字）指令的装置和方法，以及VLIW处理器和处理VLIW指令的方法，以通过VLIW指令生成指令束来配置和处理VLIW指令。 构成：指令提取单元（410）获取指令束，并且指令束是并行执行的多个指令，并且包括以束单位表示条件执行的值。 解码器（420）解码指令束。 命令执行单元（430）根据表示条件执行的值并行地执行指令包中包含的指令。 显示条件执行的值是谓词寄存器文件的索引。
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公开(公告)号：KR1020090028385A
公开(公告)日：2009-03-18
申请号：KR1020070129136
申请日：2007-12-12
Applicant: 삼성전자주식회사
CPC classification number: G06F17/5022
Abstract: An electric power simulation method and an electric power simulator are provided to improve the accuracy regardless of reducing the simulation carrying out time. A static information extracting unit(710) is the static information about the performance of a second instruction performed in a coarse grained array. That is, the static information extracting unit extracts the static information based on the configuration information of the coarse grained array. The dynamic information extracting unit(720) the dynamic information about the performance of a second instruction performed in a coarse grained array. The calculation unit(730) calculates the estimation electric power of processor based on static and dynamic information by reflecting the processing property of the processor.
Abstract translation: 提供电力模拟方法和电力模拟器，以提高精度，而不管减少模拟执行时间。 静态信息提取单元（710）是关于在粗粒度阵列中执行的第二指令的执行的静态信息。 也就是说，静态信息提取单元根据粗粒子阵列的配置信息提取静态信息。 动态信息提取单元（720）关于在粗粒度阵列中执行的第二指令的性能的动态信息。 计算单元（730）通过反映处理器的处理特性，基于静态和动态信息来计算处理器的估计电力。
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公开(公告)号：KR100879896B1
公开(公告)日：2009-01-21
申请号：KR1020070018901
申请日：2007-02-26
Applicant: 삼성전자주식회사
IPC: H04N7/01
Abstract: 본 발명은 밴드 인터리브 포맷의 영상 데이터를 밴드 분할 포맷의 영상 데이터로 변환하는 포맷 변환 장치에 관한 것으로, 밴드 인터리브 포맷(band interleave format)의 영상 데이터(image data)를 저장하는 메모리, 및 상기 메모리의 독출 주소(read address)를 스트라이드(stride)씩 증가시켜 상기 메모리를 독출하여, 상기 밴드 인터리브 포맷의 영상 데이터를 밴드 분할 포맷(band separate format)의 영상 데이터로 변환하는 변환부를 포함하는 포맷 변환 장치(format converter)를 제공한다.
밴드 인터리브 포맷(band interleave format), 밴드 분할 포맷(band separate format), SIMD-
公开(公告)号：KR1020080063697A
公开(公告)日：2008-07-07
申请号：KR1020070018901
申请日：2007-02-26
Applicant: 삼성전자주식회사
IPC: H04N7/01
CPC classification number: G06T3/606
Abstract: An apparatus for converting a band interleave format to a band separate format is provided to convert image data of the band interleave format into image data of the band separate format and perform SIMD(Single Instruction Multiple Data) mode processing after performing N partitioning of an ALU(Arithmetic and Logic Unit), thereby improving efficiency of image processing. A memory(310) stores image data of a band interleave format. A converting module reads the memory by increasing a read address of the memory as much as a stride, and converts the image data of the band interleave format into image data of a band separate format. The converting module comprises a memory controller(320) and a register filter(330). A data line(311) is branched into data lines(313,315,317,319) and respectively connected to registers(331,333,335,337) of the register file.
Abstract translation: 提供一种用于将频带交织格式转换为频带分离格式的装置，用于将频带交织格式的图像数据转换为带分离格式的图像数据，并在执行ALU的N划分之后执行SIMD（单指令多数据）模式处理 （算术和逻辑单元），从而提高图像处理的效率。 存储器（310）存储频带交织格式的图像数据。 转换模块通过增加存储器的读取地址来读取存储器，并将频带交织格式的图像数据转换为带分离格式的图像数据。 转换模块包括存储器控制器（320）和寄存器过滤器（330）。 数据线（311）分支成数据线（313,315,317,319），分别连接到寄存器文件的寄存器（331,333,335,337）。
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Patent Agency Ranking
公开(公告)号：KR1020070059238A
公开(公告)日：2007-06-12
申请号：KR1020050117868
申请日：2005-12-06
Applicant: 삼성전자주식회사
IPC: G06F13/00 , G06F15/163 , G06F15/16
CPC classification number: G06F17/5054 , G06F9/381 , G06F15/7867 , Y02D10/12 , Y02D10/13
Abstract: A device and a method for optimizing a loop buffer in a reconfigurable processor are provided to offer the reconfigurable processor not performing a delay operation in each circuit unit by using a memory storing information calculating validity to reduce access overhead and size of the loop buffer. A configuration memory(520) stores configuration bits for configuring at least one loop buffer. A validity information memory(530) stores bit information indicating whether the operations present in a loop are the delay operation. A processing unit(510) determines whether the operation corresponding to a next cycle is the delay operation by referring to bit information received from the validity information memory, and selectively changes and executes the configuration according to the configuration bits received from the configuration memory depending on a determination result. The processing unit includes the loop buffer(512), a delay controller(513), and a processing element(511). The loop buffer selectively outputs the configuration bits according to signals generated in the controller, and the processing unit changes and executes the configuration.
Abstract translation: 提供了一种用于优化可重配置处理器中的环路缓冲器的装置和方法，以通过使用存储信息计算有效性的存储器来降低存取开销和环路缓冲器的大小来提供不执行每个电路单元中的延迟操作的可重配置处理器。 配置存储器（520）存储用于配置至少一个循环缓冲器的配置位。 有效性信息存储器（530）存储指示循环中存在的操作是否为延迟操作的位信息。 处理单元（510）通过参考从有效性信息存储器接收到的位信息来确定与下一个周期相对应的操作是否是延迟操作，并且根据从配置存储器接收的配置位选择性地改变和执行配置，这取决于 确定结果。 处理单元包括循环缓冲器（512），延迟控制器（513）和处理元件（511）。 循环缓冲器根据控制器中产生的信号选择性地输出配置位，并且处理单元改变并执行配置。
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公开(公告)号：KR100662846B1
公开(公告)日：2007-01-02
申请号：KR1020050107084
申请日：2005-11-09
Applicant: 삼성전자주식회사
IPC: G06F9/38
Abstract: A system and a method for processing data are provided to efficiently use register files by dynamically adjusting the number of rotating and static registers for a software pipelined loop. A compiler(330) compiles the program by determining the number of rotating/static registers for allocating the register to variables included in a program, and allocating the register to the variables based on the determined number of rotating/static registers. A processor(100) executes the compiled program, and includes the register file(130) comprising the static/rotating registers, a special register(140) storing a value corresponding to the number of rotating registers, a processor core(110) executing a command for storing the value to the special register, and an address interpreter(120) finding a physical address from a logical address of the register based on the stored value. The number of static/rotating registers is determined to minimize generation of a spill/fill code generated during execution of the program for each loop included in the program.
Abstract translation: 通过动态调整软件流水线循环的旋转和静态寄存器的数量，提供了一种处理数据的系统和方法，以有效地使用寄存器文件。 编译器（330）通过确定用于将寄存器分配给包括在程序中的变量的旋转/静态寄存器的数量来编译程序，并且基于确定的旋转/静态寄存器的数量将寄存器分配给变量。 处理器（100）执行编译程序，并且包括包含静态/旋转寄存器的寄存器文件（130），存储与旋转寄存器的数量对应的值的特殊寄存器（140），执行 用于将该值存储到专用寄存器的命令;以及地址解释器（120），基于存储的值从寄存器的逻辑地址找到物理地址。 确定静态/旋转寄存器的数量，以最小化程序执行期间生成的溢出/填充代码，用于程序中包含的每个循环。
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公开(公告)号：KR102112522B1
公开(公告)日：2020-05-19
申请号：KR1020130050822
申请日：2013-05-06
Applicant: 삼성전자주식회사
IPC: H04N21/4788 , H04N21/426 , H04N21/422
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