Abstract:
Method and system aspects control access through a synchronization primitive to a peripheral device in a processing system. A processing system in accordance with the present invention includes at least one central processing unit (CPU), and at least one peripheral device coupled to the at least one CPU, where the at least one peripheral device includes a synchronization primitive for controlling acquisition by at least one thread of execution from the at least one CPU. In a system aspect for controlling access, the system includes a circuit for sending a first signal from a component of the processing system to a synchronization primitive within the peripheral device to determine a state of the synchronization primitive, and acquiring control of the peripheral device when the synchronization primitive is in a released state. In a method for gaining control of a peripheral device in a processing system, the method includes sending a first signal from a component of the processing system to a semaphore register within the peripheral device to determine a bit pattern in the semaphore register, and acquiring control of the peripheral device when the semaphore register stores a first bit pattern.
Abstract:
A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32, MP33), a variable input current source (Ics), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit (212). The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).
Abstract:
An ATM switch is provided with two stages of crossbar switches with internal blocking paths between the stages. To define priorities of input ports, switches of stage 1 calculate the effective serial numbers of the input ports based on their physical serial numbers and global offset values. To provide dynamic modification of the input port priorities, the global offset values can be changed in each cell cycle of the ATM switch. A sequence of encoded requests for access to required output ports are sent from each switch of stage 1 to each switch of stage 2. Contention arbitration logic in each switch of stage 2 determines which requests may be granted so as to avoid blocking paths between stages 1 and 2, and to prevent out-of-order cell delivery. Signals that acknowledge acceptance of cells and provide information required to establish the serial numbers of the accepted input ports are sent back from each switch of stage 2 to each switch of stage 1. Based on these signals, the cells that will be accepted are routed through the switches of stages 1 and 2 to required output ports. The rejected cells may be queued for transmitting in the next cell cycle.
Abstract:
An oxide protection circuit prevents failure of the MOS transistors in a digital device. A voltage difference at a gate oxide of a digital device does not exceed a breakdown voltage magnitude. The gate oxide protection circuit includes a plurality of transistors which turn OFF or ON when a node reaches a predetermined voltage of Vrefp+Vt or Vrefn-Vt, where Vrefp and Vrefn are references applied at a gate of a PMOS or an NMOS transistor, and Vt equals a threshold voltage of the MOS transistor.
Abstract:
A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.
Abstract:
A method and apparatus for generating a data signal from a transmitted data signal that has been distorted by duty cycle jitter. A locally generated symbol signal is propagated in a delay line such that taps along the delay line emit bit phase signals that are used to clock transitions of the data signal. The position of the data transitions are accorded a numerical value with reference to the bit boundaries and numerically averaged to determine a most desired time to detect the logic level of the data sample.
Abstract:
A superscalar microprocessor is provided that includes a plurality of execution units each configured to execute the same subset of instructions. The subset of instructions may include arithmetic instructions and instructions optimized for performing DSP functionality. Instructions are routed to each of the execution units from an instruction decode unit. Each execution unit includes a plurality reservation stations for storing the instructions awaiting execution. The superscalar microprocessor advantageously includes an instruction reroute unit configured to determine whether a pending instruction within a reservation station of a particular execution unit must wait for more than a predetermined number of clock cycles before the execution unit can begin its execution. Upon detecting that a pending instruction will need to wait more than the predetermined number of clock cycles before its execution can begin, the instruction reroute unit transfers the instruction to another execution unit which is not incurring an execution bottleneck condition.
Abstract:
A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.
Abstract:
A method of radio frequency communications between a first unit and a second unit. The method includes the steps of transmitting during a first time interval over a first frequency by the first unit, receiving during the first time interval over the first frequency by the second unit, transmitting during a second time interval over a second frequency by the second unit, receiving during the second time interval over the second frequency by the first unit. The method also includes the step of setting a select frequency shift between the first frequency and the second frequency. In one application of the method, the first unit is a cordless telephone hand set and the second unit is a cordless telephone base station. The method is particularly effective when the first unit and the second unit operate in TDD mode.
Abstract:
An improved dual tone multifrequency (DTMF) signal detector which uses the Goertzel DFT algorithm and which utilizes variable or differing frame widths that are frequency dependent for improved detection and reduced error. The DTMF detector includes a codec receiver which receives signals from the transmission media, and a digital signal processor (DSP) coupled to the codec. The DSP receives the digital samples and preferably applies the Goertzel DFT algorithm using differing frame lengths according to the present invention. The DTMF detector utilizes a different frame width for different tones of the possible tone frequencies according to the present invention. Thus the calculation uses a different frame length N for different ones of the uncorrelated frequencies, wherein the different frame lengths comprise at least a subset N of the number of digital samples. The different frame lengths N are designed to optimally align the calculated frequency spectrum at each of the different uncorrelated frequencies. The calculation produces an energy value for each of the different uncorrelated frequencies. The DTMF detector preferably multiplies a gain value with each of the energy values to adjust the gain of each of the energy values. After the frequency domain calculation, i.e., after energy values have been calculated for each of the different uncorrelated frequencies, and after any desired gain adjustment, the DSP determines maximum values of the energy values for each of the two or more frequency groups to detect the plurality of tones in the received signal. The DTMF detector also performs various other calculations to ensure valid tone detection.