公开(公告)号：WO1997030390A1

公开(公告)日：1997-08-21

申请号：PCT/US1996016706

申请日：1996-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROBERTS, David, G.

IPC: G06F09/46

CPC classification number: G06F9/52 ,  G06F13/126

Abstract: Method and system aspects control access through a synchronization primitive to a peripheral device in a processing system. A processing system in accordance with the present invention includes at least one central processing unit (CPU), and at least one peripheral device coupled to the at least one CPU, where the at least one peripheral device includes a synchronization primitive for controlling acquisition by at least one thread of execution from the at least one CPU. In a system aspect for controlling access, the system includes a circuit for sending a first signal from a component of the processing system to a synchronization primitive within the peripheral device to determine a state of the synchronization primitive, and acquiring control of the peripheral device when the synchronization primitive is in a released state. In a method for gaining control of a peripheral device in a processing system, the method includes sending a first signal from a component of the processing system to a semaphore register within the peripheral device to determine a bit pattern in the semaphore register, and acquiring control of the peripheral device when the semaphore register stores a first bit pattern.

Abstract translation: 方法和系统方面通过同步原语控制对处理系统中的外围设备的访问。 根据本发明的处理系统包括至少一个中央处理单元（CPU）和耦合到至少一个CPU的至少一个外围设备，其中所述至少一个外围设备包括同步原语，用于控制在 至少一个CPU执行的至少一个执行线程。 在用于控制访问的系统方面中，系统包括用于将第一信号从处理系统的组件发送到外围设备内的同步原语的电路，以确定同步原语的状态，以及获取外围设备的控制 同步原语处于释放状态。 在一种用于在处理系统中获得对外围设备的控制的方法中，所述方法包括将来自所述处理系统的组件的第一信号发送到所述外围设备内的信号量寄存器，以确定所述信号量寄存器中的位模式，以及获取控制 的信号量寄存器存储第一位模式。

公开(公告)号：WO1997030384A1

公开(公告)日：1997-08-21

申请号：PCT/US1996016705

申请日：1996-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RUNALDUE, Thomas, J.

IPC: G05F03/26

CPC classification number: G05F3/262

Abstract: A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32, MP33), a variable input current source (Ics), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit (212). The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).

Abstract translation: 用于在CMOS集成电路技术中用于镜像电流的电流镜电路包括由第一和第二P沟道MOS晶体管（MP32，MP33），可变输入电流源（Ics），第一源极跟随器晶体管（MN34） ，第二源极跟随器晶体管（MP35），电流吸收晶体管（MN31）和负载电路（212）。 负载电路由负载晶体管（MN36）和负载电阻（R1）构成。 在替代实施例中，负载电路由单个负载电阻器形成。 结果，注入第一P沟道MOS晶体管（MP32）的电流量更精确地镜像到第二P沟道MOS晶体管（MP33）中。

公开(公告)号：WO1997029574A1

公开(公告)日：1997-08-14

申请号：PCT/US1996018087

申请日：1996-11-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RUNALDUE, Thomas, J.

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/1553 ,  H04L49/1561 ,  H04L49/255 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: An ATM switch is provided with two stages of crossbar switches with internal blocking paths between the stages. To define priorities of input ports, switches of stage 1 calculate the effective serial numbers of the input ports based on their physical serial numbers and global offset values. To provide dynamic modification of the input port priorities, the global offset values can be changed in each cell cycle of the ATM switch. A sequence of encoded requests for access to required output ports are sent from each switch of stage 1 to each switch of stage 2. Contention arbitration logic in each switch of stage 2 determines which requests may be granted so as to avoid blocking paths between stages 1 and 2, and to prevent out-of-order cell delivery. Signals that acknowledge acceptance of cells and provide information required to establish the serial numbers of the accepted input ports are sent back from each switch of stage 2 to each switch of stage 1. Based on these signals, the cells that will be accepted are routed through the switches of stages 1 and 2 to required output ports. The rejected cells may be queued for transmitting in the next cell cycle.

Abstract translation: ATM交换机具有两级交叉开关，其中两级之间具有内部阻塞路径。 为了确定输入端口的优先级，阶段1的开关根据其物理序列号和全局偏移量计算输入端口的有效序列号。 为了提供对输入端口优先级的动态修改，可以在ATM交换机的每个单元周期中改变全局偏移值。 从阶段1的每个交换机向阶段2的每个交换机发送用于访问所需输出端口的编码请求序列。阶段2的每个交换机中的争用仲裁逻辑确定可以授予哪些请求，以避免在阶段1之间阻塞路径 和2，并且防止无序细胞递送。 确认接收单元并提供建立接受的输入端口的序列号所需的信息的信号从阶段2的每个开关发送回到阶段1的每个开关。基于这些信号，被接收的单元被路由通过 阶段1和2的开关到所需的输出端口。 被拒绝的小区可以排队等待在下一个小区周期中进行传输。

公开(公告)号：WO1997029544A1

公开(公告)日：1997-08-14

申请号：PCT/US1996015029

申请日：1996-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MALEY, Reading

IPC: H03K19/003

CPC classification number: H03K19/00315

Abstract: An oxide protection circuit prevents failure of the MOS transistors in a digital device. A voltage difference at a gate oxide of a digital device does not exceed a breakdown voltage magnitude. The gate oxide protection circuit includes a plurality of transistors which turn OFF or ON when a node reaches a predetermined voltage of Vrefp+Vt or Vrefn-Vt, where Vrefp and Vrefn are references applied at a gate of a PMOS or an NMOS transistor, and Vt equals a threshold voltage of the MOS transistor.

Abstract translation: 氧化物保护电路防止数字装置中的MOS晶体管的故障。 数字装置的栅极氧化物处的电压差不超过击穿电压的大小。 栅极氧化物保护电路包括当节点达到Vrefp + Vt或Vrefn-Vt的预定电压时关断或导通的多个晶体管，其中Vrefp和Vrefn是在PMOS或NMOS晶体管的栅极处施加的基准，以及 Vt等于MOS晶体管的阈值电压。

公开(公告)号：WO1997029418A1

公开(公告)日：1997-08-14

申请号：PCT/US1996017305

申请日：1996-10-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RUNALDUE, Thomas, J. ,  CHENG, Yi

IPC: G06F01/02

CPC classification number: H04L25/03834 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0321

Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

Abstract translation: 一种用于合成波形的系统包括：波形合成电路，其生成具有在零交叉处具有预选斜率的一组波形脉冲中的每一个的数字数据。 定序器跟踪包含在数据信号中的信息的历史，并响应于历史选择一个波形脉冲序列，使得序列传送信息历史，同时使序列中相邻波形脉冲的斜率最小化。

公开(公告)号：WO1997028624A1

公开(公告)日：1997-08-07

申请号：PCT/US1996018274

申请日：1996-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BEHRIN, Michael, N.

IPC: H04L07/033

CPC classification number: H04L7/0338 ,  H04L7/0337

Abstract: A method and apparatus for generating a data signal from a transmitted data signal that has been distorted by duty cycle jitter. A locally generated symbol signal is propagated in a delay line such that taps along the delay line emit bit phase signals that are used to clock transitions of the data signal. The position of the data transitions are accorded a numerical value with reference to the bit boundaries and numerically averaged to determine a most desired time to detect the logic level of the data sample.

Abstract translation: 一种用于通过占空比抖动而被发送的数据信号产生数据信号的方法和装置。 本地产生的符号信号在延迟线中传播，使得沿着延迟线的抽头发射用于对数据信号的时钟转换进行时钟转换的位相位信号。 参考位边界将数据转换的位置赋予数值，并对其进行数值平均，以确定检测数据样本的逻辑电平的最理想时间。

公开(公告)号：WO1997025671A1

公开(公告)日：1997-07-17

申请号：PCT/US1996020045

申请日：1996-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  IRETON, Mark, A.

IPC: G06F09/38

CPC classification number: G06F9/3857 ,  G06F9/3836 ,  G06F9/3855

Abstract: A superscalar microprocessor is provided that includes a plurality of execution units each configured to execute the same subset of instructions. The subset of instructions may include arithmetic instructions and instructions optimized for performing DSP functionality. Instructions are routed to each of the execution units from an instruction decode unit. Each execution unit includes a plurality reservation stations for storing the instructions awaiting execution. The superscalar microprocessor advantageously includes an instruction reroute unit configured to determine whether a pending instruction within a reservation station of a particular execution unit must wait for more than a predetermined number of clock cycles before the execution unit can begin its execution. Upon detecting that a pending instruction will need to wait more than the predetermined number of clock cycles before its execution can begin, the instruction reroute unit transfers the instruction to another execution unit which is not incurring an execution bottleneck condition.

Abstract translation: 提供了一种超标量微处理器，其包括多个执行单元，每个执行单元被配置为执行相同的指令子集。 指令子集可以包括优化用于执行DSP功能的算术指令和指令。 指令从指令解码单元路由到每个执行单元。 每个执行单元包括用于存储等待执行的指令的多个预留站。 超标量微处理器有利地包括指令重新路由单元，其被配置为在执行单元可以开始执行之前确定特定执行单元的保留站内的未决指令是否必须等待多于预定数量的时钟周期。 一旦检测到待执行的指令将需要等待超过预定数量的时钟周期才能开始执行，则指令重新路由单元将该指令传送到不产生执行瓶颈条件的另一个执行单元。

公开(公告)号：WO1997023044A1

公开(公告)日：1997-06-26

申请号：PCT/US1996012252

申请日：1996-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHRAPE-GEISLER, Bradley, A.

IPC: H03K19/00

CPC classification number: H03K19/0027 ,  H03K19/00323

Abstract: A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.

Abstract translation: 一种缓冲器，其提供由高密度可编程逻辑器件（PLD）的开关矩阵引入的RC时间延迟的补偿。 缓冲器包括提供输入阈值的电路，其变化以补偿在高到低输入信号转换时开关矩阵的RC延迟。 该缓冲器还包括一个负的滞后电路，以防止在慢速率低到高输入信号转换时的振荡。

公开(公告)号：WO1997021287A1

公开(公告)日：1997-06-12

申请号：PCT/US1996013534

申请日：1996-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MAGNA, Javier, V.

IPC: H04B07/26

CPC classification number: H04B7/2621 ,  H04B7/2615

Abstract: A method of radio frequency communications between a first unit and a second unit. The method includes the steps of transmitting during a first time interval over a first frequency by the first unit, receiving during the first time interval over the first frequency by the second unit, transmitting during a second time interval over a second frequency by the second unit, receiving during the second time interval over the second frequency by the first unit. The method also includes the step of setting a select frequency shift between the first frequency and the second frequency. In one application of the method, the first unit is a cordless telephone hand set and the second unit is a cordless telephone base station. The method is particularly effective when the first unit and the second unit operate in TDD mode.

Abstract translation: 一种在第一单元和第二单元之间的射频通信的方法。 该方法包括以下步骤：在第一时间间隔内通过第一单元在第一时间间隔内发送，在第一时间间隔期间通过第二单元接收第一时间间隔，在第二时间间隔期间通过第二单元在第二时间间隔内传输第二频率 ，在所述第二频率的所述第二时间间隔期间由所述第一单元接收。 该方法还包括在第一频率和第二频率之间设置选择频移的步骤。 在该方法的一个应用中，第一单元是无绳电话手机，第二单元是无绳电话基站。 当第一单元和第二单元以TDD模式工作时，该方法特别有效。

公开(公告)号：WO1997020438A1

公开(公告)日：1997-06-05

申请号：PCT/US1996016492

申请日：1996-10-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  XIE, Zheng-yi ,  BARTKOWIAK, John, G.

IPC: H04Q01/457

CPC classification number: H04Q1/453 ,  H04M7/1295 ,  H04Q1/457

Abstract: An improved dual tone multifrequency (DTMF) signal detector which uses the Goertzel DFT algorithm and which utilizes variable or differing frame widths that are frequency dependent for improved detection and reduced error. The DTMF detector includes a codec receiver which receives signals from the transmission media, and a digital signal processor (DSP) coupled to the codec. The DSP receives the digital samples and preferably applies the Goertzel DFT algorithm using differing frame lengths according to the present invention. The DTMF detector utilizes a different frame width for different tones of the possible tone frequencies according to the present invention. Thus the calculation uses a different frame length N for different ones of the uncorrelated frequencies, wherein the different frame lengths comprise at least a subset N of the number of digital samples. The different frame lengths N are designed to optimally align the calculated frequency spectrum at each of the different uncorrelated frequencies. The calculation produces an energy value for each of the different uncorrelated frequencies. The DTMF detector preferably multiplies a gain value with each of the energy values to adjust the gain of each of the energy values. After the frequency domain calculation, i.e., after energy values have been calculated for each of the different uncorrelated frequencies, and after any desired gain adjustment, the DSP determines maximum values of the energy values for each of the two or more frequency groups to detect the plurality of tones in the received signal. The DTMF detector also performs various other calculations to ensure valid tone detection.

Abstract translation: 改进的双音多频（DTMF）信号检测器，其使用Goertzel DFT算法，并且利用与频率相关的可变或不同的帧宽度来改善检测和减少误差。 DTMF检测器包括从传输介质接收信号的编解码器接收器和耦合到编解码器的数字信号处理器（DSP）。 DSP接收数字样本，并且优选地根据本发明应用使用不同帧长度的Goertzel DFT算法。 根据本发明，DTMF检测器对于可能的音调频率的不同音调使用不同的帧宽度。 因此，不同的不相关频率的计算使用不同的帧长度N，其中不同的帧长度至少包括数字样本数量的子集N。 不同的帧长度N被设计成在每个不相关的频率下优化对准所计算的频谱。 该计算产生每个不相关频率的能量值。 DTMF检测器优选地将增益值与每个能量值相乘以调整每个能量值的增益。 在频域计算之后，即，在针对每个不相关的频率计算能量值之后，并且在任何期望的增益调整之后，DSP确定两个或更多个频率组中的每一个的能量值的最大值，以检测 接收信号中的多个音调。 DTMF检测器还执行各种其他计算，以确保有效的音调检测。