公开(公告)号：US20230299668A1

公开(公告)日：2023-09-21

申请号：US18323304

申请日：2023-05-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

CPC classification number: H02M3/07 ,  G05F3/10 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/17 ,  H01L29/66181 ,  H01L2224/02379

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US11735567B2

公开(公告)日：2023-08-22

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/32 ,  H01L23/481 ,  H01L23/60 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/30205

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20220293433A1

公开(公告)日：2022-09-15

申请号：US17460806

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US20220285273A1

公开(公告)日：2022-09-08

申请号：US17699563

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20220014095A1

公开(公告)日：2022-01-13

申请号：US17383983

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US20210242170A1

公开(公告)日：2021-08-05

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20200176419A1

公开(公告)日：2020-06-04

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20190189560A1

公开(公告)日：2019-06-20

申请号：US16250854

申请日：2019-01-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Huabo Chen ,  Zhenggang Cheng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/14

Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

公开(公告)号：US10217708B1

公开(公告)日：2019-02-26

申请号：US15845978

申请日：2017-12-18

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Huabo Chen ,  Zhenggang Cheng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065

Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

公开(公告)号：US09607680B2

公开(公告)日：2017-03-28

申请号：US14196793

申请日：2014-03-04

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: G11C11/4074 ,  H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L27/108 ,  H01L49/02 ,  H01L23/498 ,  G11C7/02 ,  G11C5/14 ,  G11C29/02 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C7/02 ,  G11C14/0018 ,  G11C29/021 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.