公开(公告)号：GB2447795A

公开(公告)日：2008-09-24

申请号：GB0807135

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). A random or predetermined number of pseudo instructions are inserted into an encryption algorithm such that the leaked information cannot be aligned in time to allow an attacker to break the encryption. The pseudo instructions mimic real instructions in terms of energy consumption without affecting the running of the encryption algorithm. The algorithm may be a Data Encryption Standard (DES) algorithm and the pseudo instructions may emulate bit-wise shift instructions. The pseudo instructions may be inserted in substitution/permutation box entry address evaluations. The pseudo instructions may be performed when a control flag is set, the control flag halting a state machine of a processor running the encryption algorithm. The halting of the state machine may comprise disabling a destination register of the state machine. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver.

公开(公告)号：GB2430800A

公开(公告)日：2007-04-04

申请号：GB0622262

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The spacing between the source/drain and gate electrodes of a non-operable MOSFET is set to a distance equal to a sidewall spacer to increase the similarity between non-operable and operable devices. The device structure inhibits attempts at reverse engineering.

公开(公告)号：GB2410835B

公开(公告)日：2007-01-17

申请号：GB0508291

申请日：2003-09-23

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：GB2422956A

公开(公告)日：2006-08-09

申请号：GB0608053

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The distance between the gate and source/drain of a non-operable FET is defined by a block mask to be the same as the distance between the gate and source/drain of an operable FET which is defined by a gate sidewall spacer. The camouflaged non-operable circuit structure inhibits attempts at reverse engineering.

公开(公告)号：GB2411293B

公开(公告)日：2006-07-12

申请号：GB0510347

申请日：2003-10-16

Applicant: HRL LAB LLC ,  PROMTEK

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  YANG PAUL OU

IPC: H01L27/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L29/40

Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.

公开(公告)号：AU4244000A

公开(公告)日：2000-11-10

申请号：AU4244000

申请日：2000-04-14

Applicant: HRL LAB LLC ,  HUGHES ELECTRONICS CORP

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092

Abstract: A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.