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公开(公告)号:CA1033463A
公开(公告)日:1978-06-20
申请号:CA284557
申请日:1977-08-12
Applicant: IBM
Inventor: CHANG HSU , LEE SHARE-YOUNG
IPC: G06F7/22
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公开(公告)号:CA1019064A
公开(公告)日:1977-10-11
申请号:CA195119
申请日:1974-03-15
Applicant: IBM
Inventor: CHANG HSU , CHEN TIEN CHI , TUNG CHIN
IPC: G06F7/48 , G11C11/14 , H03K19/168
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公开(公告)号:DE2509511A1
公开(公告)日:1975-09-11
申请号:DE2509511
申请日:1975-03-05
Applicant: IBM
Inventor: CHANG HSU
Abstract: A bubble domain lattice system in which information exists as the presence and absence of bubble domains. A lattice exists in a conveyor layer and lattice bubble domains are coupled (magnetostatically or by exchange forces) to information bubble domains in another magnetic layer (information layer). These information bubble domains are coded in accordance with their presence or absence in the information layer. When the bubble lattice domains in the conveyor layer are moved, corresponding bubble domains in the information layer move in a similar manner, due to the magnetostatic coupling. Consequently, the high density advantages of a lattice arrangement are achieved in the present system, while coding of information is achieved without having to require different types of magnetic bubble domains.
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公开(公告)号:CA960359A
公开(公告)日:1974-12-31
申请号:CA130918
申请日:1971-12-23
Applicant: IBM
Inventor: CHANG HSU , GENOVESE EUGENE R
IPC: G11C19/08 , H03K19/168 , H03M7/00
Abstract: A complete on-chip memory system for cylindrical bubble domains and a magnetic chip decoder for the system. Write and read decoding, memory storage, and sensing are provided on a single magnetic chip with a minimum number of interconnections and ease of fabrication. Decoding is achieved using magnetic overlays for propagation and current loops to provide selective switching at various locations. N control lines enable selective connections between 2N domain generators and 2N shift registers. The decoders have 2N double propagation channels, each of which has two parallel paths. One path connects a generator to a shift register while the other path terminates in a bubble buster. Each shift register comprises a storage loop having bubble splitters, thus enabling NDRO. The storage loops are connected to a double propagation channel in a read decoder. Sensing means are connected to the output of the read decoder.
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公开(公告)号:CA939059A
公开(公告)日:1973-12-25
申请号:CA145366
申请日:1972-06-22
Applicant: IBM
Inventor: KEEFE G , CHANG HSU , ROSIER L , LIN YEONG S
Abstract: A decoder for cylindrical magnetic domain shift registers having means to clear the information from selected registers thus enabling new information to be written into those registers. The decoder is incorporated into 2N closed loop shift registers and uses only a small part of the storage area of the magnetic sheet in which domains exist. It is activated by 2N control lines (N pairs). Depending upon the activation of the decoder, the information in a selected shift register is passed to a clear means which sends it into one of two paths depending upon the activation of the clear means. One path brings the information to a detector for destructive readout, while the other path brings the information to a domain splitter. The domain splitter splits the input domains into two parts, one of which propagates to the detector while the other returns to the proper shift register. Thus, non-destructive readout (NDRO) or destructive read-out (DRO) is provided depending upon the activation of the clear means.
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公开(公告)号:DE2227007A1
公开(公告)日:1973-01-11
申请号:DE2227007
申请日:1972-06-02
Applicant: IBM
Inventor: CHANG HSU , KEEFE GEORGE EDWARD , LIN YEONG SHOW , ROSIER LAURENCE LEE
Abstract: A decoder for cylindrical magnetic domain shift registers having means to clear the information from selected registers thus enabling new information to be written into those registers. The decoder is incorporated into 2N closed loop shift registers and uses only a small part of the storage area of the magnetic sheet in which domains exist. It is activated by 2N control lines (N pairs). Depending upon the activation of the decoder, the information in a selected shift register is passed to a clear means which sends it into one of two paths depending upon the activation of the clear means. One path brings the information to a detector for destructive readout, while the other path brings the information to a domain splitter. The domain splitter splits the input domains into two parts, one of which propagates to the detector while the other returns to the proper shift register. Thus, non-destructive readout (NDRO) or destructive read-out (DRO) is provided depending upon the activation of the clear means.
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