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    41.
    发明专利
    未知

    公开(公告)号：DE3382179D1

    公开(公告)日：1991-04-04

    申请号：DE3382179

    申请日：1983-12-21

    Applicant: IBM

    Inventor： CARRUBBA FRANK PAUL ,  COCKE JOHN ,  KREITZER NORMAN ,  RADIN GEORGE

    IPC: G06F12/08 ,  G06F12/12

    Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement with the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory. … The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Moditication of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted. … The cache architecture and controls permit normal instruction and data cache fetches and data cache stores. Additionally, special instructions are provided for setting the special control bits provided in both the instruction and data cache directories, independently of actual memory accessing OPS by the CPU and for storing and loading cache lines independently of memory OPS by the CPU.

    INTERCONNECT SCHEME FOR SHARED MEMORY LOCAL NETWORKS
    44.
    发明专利
    INTERCONNECT SCHEME FOR SHARED MEMORY LOCAL NETWORKS 未知

    公开(公告)号：CA1229422A

    公开(公告)日：1987-11-17

    申请号：CA481723

    申请日：1985-05-16

    Applicant: IBM

    Inventor： COCKE JOHN ,  HAILPERN BRENT T ,  HOEVEL LEE W ,  SHAPIRO EUGENE ,  BLOUNT MARION L

    IPC: G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/173

    Abstract: INTERCONNECT SCHEME FOR SHARED MEMORY LOCAL NETWORKS A plurality of intelligent work stations are provided access to a shared memory through a switching hierachy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.

    HIERARCHICAL MEMORY SYSTEM INCLUDING SEPARATE CACHE MEMORIES FOR STORING DATA AND INSTRUCTIONS
    45.
    发明专利
    HIERARCHICAL MEMORY SYSTEM INCLUDING SEPARATE CACHE MEMORIES FOR STORING DATA AND INSTRUCTIONS 未知

    公开(公告)号：CA1199420A

    公开(公告)日：1986-01-14

    申请号：CA443643

    申请日：1983-12-19

    Applicant: IBM

    Inventor： CARRUBBA FRANCIS P ,  COCKE JOHN ,  KREITZER NORMAN H ,  RADIN GEORGE

    IPC: G06F12/08 ,  G06F12/12

    Abstract: A HIERARCHICAL MEMORY SYSTEM INCLUDING SEPARATE CACHE MEMORIES FOR STORING DATA AND INSTRUCTIONS A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement within the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory.

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