公开(公告)号：GB2488259A

公开(公告)日：2012-08-22

申请号：GB201207123

申请日：2010-12-09

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS S ,  HAAS ROBERT ,  HU XIAO-YU

IPC: G06F13/16

Abstract: A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.

公开(公告)号：GB2488057A

公开(公告)日：2012-08-15

申请号：GB201207470

申请日：2010-11-26

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE A ,  CIDECIYAN ROY D ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAO-YU ,  ILIADIS ILIAS

IPC: G06F11/10 ,  G11C29/00

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.