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公开(公告)号：CA2780258A1
公开(公告)日：2011-06-03
申请号：CA2780258
申请日：2010-11-05
Applicant: IBM
Inventor： KATAYAMA YASUNAO , NEGISHI YASUSHI , OKAZA-KI ATSUYA
Abstract: Disclosed is a system that enables efficient packet communication by exclusively transmitting and receiving a plurality of packets in space-time. Also disclosed is a communication method therefor. The system is provided with a plurality of nodes (100 to 190) that perform wireless communication, wherein the nodes store routing information, transmit and receive packets with directivity to and from transfer origin and transfer destination nodes upon a transmission path determined from the routing information by controlling the phase of the transmitted and received waves, and perform cut-through transmission. In the system, the phase of the transmitted and received waves is controlled during a given length of time in a manner such that all nodes form at least one closed loop, and time synchronization and the transmission and reception of packet communication history are performed by means of cut-through transmission. During all other time periods, the nodes transmit and receive packets in accordance with the routing information from the nodes that is updated on the basis of the time-synchronized packet communication history shared between nodes, and in accordance with the time frame in which the transmission and reception of packets that have been distributed to the nodes is possible.
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公开(公告)号：ES2167515T3
公开(公告)日：2002-05-16
申请号：ES96300716
申请日：1996-02-01
Applicant: IBM
Inventor： KATAYAMA YASUNAO
Abstract: A memory cell comprises at least three conducting layers (20) spaced with insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunnelling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunnelling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made. This provides a storage method of a static memory using a quantum device and a structure therefor. A memory cell according to the present invention has a structure simpler than static memories being presently used. Also, an area that this structure is substantially equal to the cell area of a DRAM. Further, since the circuit is complementary, a standby current can greatly be reduced.
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公开(公告)号：DE69618044D1
公开(公告)日：2002-01-31
申请号：DE69618044
申请日：1996-02-01
Applicant: IBM
Inventor： KATAYAMA YASUNAO
Abstract: A memory cell comprises at least three conducting layers (20) spaced with insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunnelling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunnelling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made. This provides a storage method of a static memory using a quantum device and a structure therefor. A memory cell according to the present invention has a structure simpler than static memories being presently used. Also, an area that this structure is substantially equal to the cell area of a DRAM. Further, since the circuit is complementary, a standby current can greatly be reduced.
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Patent Agency Ranking
公开(公告)号：BR112013023192B1
公开(公告)日：2022-03-29
申请号：BR112013023192
申请日：2012-03-02
Applicant: IBM
Inventor： NAKANO DAIJU , KATAYAMA YASUNAO , KOHDA YASUTERO
IPC: H04B7/005
Abstract: compensação on-the-fly de frequência de amostragem e deslocamento de fase no receptor realizando comunicação sem fio de velocidade ultra alta. problema: para restaurar dados de uma sequência de símbolos transmitida sem alinhar o relógio do receptor com o relógio do transmissor. solução: os dados recebidos sobre amostrados duas vezes são polifaseados pelo receptor, o feedback é aplicado usando um algoritmo adaptativo, e os coeficientes de filtro (sequência de coeficiente de tap) de um filtro de compensação são simultaneamente deslocados quando os dados deslocam-se. a frequência de amostragem e o deslocamento de fase podem ser compensados em tempo real usando um filtro combinando um filtro afunilado, cujo valor inicial é um valor de correlação obtido a partir do preâmbulo e do cabeçalho de um sinal recebido, e um alinhador de frente de onda. nesta configuração, um circuito de filtro de reamostragem, um circuito de filtro de equalização e um circuito de filtro de dizimação são realizados em um único circuito de filtro de compensação, o que é muito menor do que os circuitos da técnica anterior, em termos de tamanho.
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公开(公告)号：CA2780258C
公开(公告)日：2018-03-13
申请号：CA2780258
申请日：2010-11-05
Applicant: IBM
Inventor： KATAYAMA YASUNAO , NEGISHI YASUSHI , OKAZA-KI ATSUYA
Abstract: To provide a system and a communication method which enable efficient packet communication by transmitting and receiving multiple packets exclusively in time and space. [Solving means] The system includes multiple nodes performing radio communication. Each node stores routing information therein, and determines a transmission path by use of the routing information, and performs cut-through transmission by transmitting and receiving packets to a transfer destination node and from a transfer source node on the determined transmission path through transmission and reception radio waves each given a certain directivity by controlling their phases. In the system, time synchronization and transmission and reception of packet communication records are performed during a certain time period by carrying out the cut-through transmission while controlling the phases of the transmission and reception radio waves so that all of the nodes form one or more closed loops. At a time other than the certain time period, the node transmits and receives packets in accordance with the routing information and a time frame assigned to each of the nodes as a time when the each node is allowed to transmit and receive a packet, the routing information held in each of the nodes and updated on the basis of the packet communication records whose information is shared by the nodes after the time synchronization.
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公开(公告)号：AU2012227102B2
公开(公告)日：2015-11-19
申请号：AU2012227102
申请日：2012-03-02
Applicant: IBM
Inventor： NAKANO DAIJU , KATAYAMA YASUNAO , KOHDA YASUTERU
IPC: H04B7/005
Abstract: The present invention restores data of a series of symbols transmitted into a receiver, without making the clock of the receiver match the clock of a transmitter. In this receiver, received data that was over-sampled by two times is made into polyphase, and the data is shifted and a filter coefficient (a series of tap coefficients) of a compensation filter is shifted at the same time, by applying a feedback of an adaptation algorithm. Sampling frequency and phase offset can be compensated on-the-fly, by making a received signal pass through a filter that is a combination of a tapped filter, which has a correlation value obtained from a preamble or a header of the received signal set as the initial value thereof, and a wavefront aligner (a wavefront matching-box). Such a configuration is equivalent to achieving a resampling filter circuit, an equivalent filter circuit, and a decimation filter circuit with just one compensation filter circuit, and is able to make dimensions of a circuit far smaller than those in prior art.
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公开(公告)号：DE69618044T2
公开(公告)日：2002-08-29
申请号：DE69618044
申请日：1996-02-01
Applicant: IBM
Inventor： KATAYAMA YASUNAO
Abstract: A memory cell comprises at least three conducting layers (20) spaced with insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunnelling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunnelling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made. This provides a storage method of a static memory using a quantum device and a structure therefor. A memory cell according to the present invention has a structure simpler than static memories being presently used. Also, an area that this structure is substantially equal to the cell area of a DRAM. Further, since the circuit is complementary, a standby current can greatly be reduced.
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公开(公告)号：DE69125542D1
公开(公告)日：1997-05-15
申请号：DE69125542
申请日：1991-07-26
Applicant: IBM
Inventor： KATAYAMA YASUNAO , KIRIHATA TOSHIAKI , SCHEUERLEIN ROY E
IPC: G11C11/409 , G11C11/4091
Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.
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