公开(公告)号：JP2003216442A

公开(公告)日：2003-07-31

申请号：JP2002008904

申请日：2002-01-17

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI

IPC: G06F9/44 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To effectively perform a scalar replacement without performing analysis in a method when a program is optimized. SOLUTION: This program converting method comprises a code converting part 110 for creating a machine language code on the basis of a source code of an execution program as a processed object, an optimizing range determining part 120 for determining a range where the object created in a method does not escape, with respect to the method in the execution program by the machine language code, and a scalar replacement executing part 130 for performing the scalar replacement within the range where the object does not escape. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002149416A

公开(公告)日：2002-05-24

申请号：JP2000331427

申请日：2000-10-30

Applicant: IBM

Inventor： INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/38 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To make effectively obtainable the instruction level parallelism of a program including an exception generable instruction by relaxing the preceding constraint of the exception generation validation instruction to the other instruction like software. SOLUTION: This compiler is provided with a DAG generating part 21 for generating a DAG by analyzing the four sets of intermediate codes of a program to be processed, a DAG editing part 22 for editing the generated DAG, and relaxing the sequence constraint of operators due to exceptions, and a four set of intermediate code reproducing part 23 for generating the four sets of intermediate codes on which the structure of the edited DAG is reflected. Then, an exception generable instruction and an exception generation detection instruction are detected from the DAG, and the detected exception generation detection instruction is divided into a first instruction for detecting the generation condition of exceptions and a second instruction for conditionally branching the processing to the exception processing. Then, dependency is set so that when the generation condition of the exceptions is detected in response to the first instruction, its transition to the second instruction can be performed, and when the generation condition of exceptions is not detected, its transition to the exception generable instruction can be performed.

公开(公告)号：JP2002116916A

公开(公告)日：2002-04-19

申请号：JP2000304618

申请日：2000-10-04

Applicant: IBM

Inventor： TABATA KUNIO ,  KOMATSU HIDEAKI

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To improve the execution efficiency of a program by appropriately dividing the program into hyper blocks at a high speed. SOLUTION: This compiler is provided with a basic block code scheduler 21 for estimating execution time with a basic block as a unit for the program of a processing object, a hyper block generation part 22 for gathering the basic blocks into the hyper block which is a parallel execution area and an execution time estimation part 23. In the case that the connection of the basic blocks is accompanied by conditional branching, the execution time estimation part 23 estimates the execution time in the case of performing execution while keeping the conditional branching as it is and in the case of parallelly executing a conditional branching part based on the execution time estimated by the basic block unit. The hyper block generation part 22 defines the part as one set of the parallel execution area in the case that the execution time is shorter in the case of parallelly executing it and divides the part into the plural parallel execution areas connected by the conditional branching in the case that the execution time is shorter in the case of performing the execution while keeping the conditional branching as it is.

公开(公告)号：JP2000222219A

公开(公告)日：2000-08-11

申请号：JP1794399

申请日：1999-01-27

Applicant: IBM

Inventor： KOSEKI SATOSHI ,  INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/00 ,  G06F9/44 ,  G06F9/445 ,  G06F9/46 ,  G06F12/02

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for processing a multidimensional array object capable of improving the processing speed of multidimensional disposition without the change of a specification. SOLUTION: The object of the processing method of this multidimensional array object is the processing method of the multidimensional object in a language (Java, e.g.) where the multidimensional array is realized by the array of array objects. The multidimensional array object consisting of the array object constituting the multidimensional array is added with a processing optimization possible flag showing that processing to the element of the multidimensional array can be optimized as additional information. The processing optimization possible flag is stored in a storing device (a main memory e.g.). After then, a machine code corresponding to the state of the processing optimization possible flag is executed.

公开(公告)号：JP2000122875A

公开(公告)日：2000-04-28

申请号：JP29629398

申请日：1998-10-19

Applicant: IBM

Inventor： ISHIZAKI KAZUAKI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/46 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To provide an exception processing instruction generating method which does not execute an unneeded instruction and its system. SOLUTION: This method reads an intermediate code of a compiler, extracts one intermediate code (110), decides whether the extracted intermediate code is an instruction needing exception check and generates exception check instruction having a bit string that is uniquely decided from an exception kind (150) without generating an instruction for substituting a label showing the exception kind for a register when the instruction needs the exception check. Then, a processor instruction corresponding to the extracted intermediate code is generated (130), and an exception processing instruction is generated by repeating the above processing while an intermediate code to be processed remains. Further, the exception check instruction to be generated checks whether an exception condition is established and when it is established, it is made into an instruction to be branched to an exception processing part.

公开(公告)号：JPH0962639A

公开(公告)日：1997-03-07

申请号：JP21560195

申请日：1995-08-24

Applicant: IBM JAPAN

Inventor： ISHIZAKI KAZUAKI ,  KOMATSU HIDEAKI ,  OGASAWARA TAKESHI

IPC: G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To speed up a communication between processors by comparing parameters based upon the execution of an execution-time code with parameters stored in a work area, and making the processors communicate with each other by reusing a communication pattern or memory access pattern according to the comparison result. SOLUTION: It is analyzed whether or not a communication pattern when a loop nest is executed can be cached (step 11) and a plurality of parameters determining the communication pattern between the processors is extracted (steps 12 and 13). Then the current parameters in the work area and old parameters stored in the work area are compared with each other (step 14), it is checked whether or not cached data are the same according to the comparison result (step 15), and the communication pattern or memory access pattern is reused to carry out the communication between the processors (steps 16-18). Consequently, the communication between the processors can be speeded up.

公开(公告)号：JPH08185325A

公开(公告)日：1996-07-16

申请号：JP31176494

申请日：1994-12-15

Applicant: IBM

Inventor： OGASAWARA TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F9/38 ,  G06F9/45 ,  G06F15/16

Abstract: PURPOSE: To parallelize a loop provided with characteristics for satisfying a condition that an index set is distributable but not satisfying the condition that the data dependency of a substitutive sentence right side is decided to be one. CONSTITUTION: Since an (x) is a variable not decided at the time of compilation, doi=M, N, a (i)=a (x) and enddo are not parallelized by a conventional technique. Then, corresponding to the large/small relation of M, N and (x), the index set of (i)=M..N including (x) is distributed to plural processors and thus, a processor set for using a value defined before the loop and the processor set for using the value defined after the loop are calculated and codes for making communication to the processors be performed are inserted before and after the loop. Thus, the need for performing the communication between the processors inside the loop is eliminated and thus, the speed of an execution program is accelerated.

公开(公告)号：JPH0695919A

公开(公告)日：1994-04-08

申请号：JP19960592

申请日：1992-07-27

Applicant: IBM

Inventor： KOMATSU HIDEAKI ,  GODA OSAMU

IPC: G06F11/28 ,  G06F9/455

Abstract: PURPOSE: To optimize emulation of memory access to increase the entire emulation speed. CONSTITUTION: Based on a conventional technique where an attribute table corresponding to one byte of a memory is provided to increase the speed, it is noticed that almost all memory operations are used for data load/store, and almost all memory operation instructions are executed without testing attribute values. The memory space is divided into segments having a certain size, and one segment prediction bit which expresses OR of attribute values of each segment is generated, and OR between the prediction bit of a pertinent segment and those of two adjacent segments is operated. This operation is executed for all of the memory space to generate a segment prediction table. Values '0' of prediction bits stored in this table mean that any memory belonging to segments corresponding to these prediction bits is used for normal memory and the test of each attribute is unnecessary.

公开(公告)号：JP2012088951A

公开(公告)日：2012-05-10

申请号：JP2010235295

申请日：2010-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAGAI SHINGO ,  OSAWA FUMITOMO ,  KOMATSU HIDEAKI

IPC: G06F11/28

CPC classification number: G06F17/5009 ,  G05B17/02 ,  G06F17/5095

Abstract: PROBLEM TO BE SOLVED: To improve the speed of simulation by predicting an output timing of an ISS and an input timing from a peripheral corresponding to the output timing.SOLUTION: The program code of an ISS216 is analyzed, and an I/O instruction arrival prediction time is estimated for each program counter and recorded with the type of an I/O instruction to be output at that time in a first stage table 206. A scheduler is configured to draw the first stage table with a value of the program counter of its execution via the ISS to acquire the information of the I/O instruction arrival prediction time and the I/O instruction to be output at that time. Furthermore, the scheduler is configured to draw a second stage table 212 in response to an I/O instruction to acquire the fastest event time from a peripheral. The scheduler is configured to know the time of an event which occurs in the closest future among a plant simulator, peripheral simulator, and ISS by using those pieces of information, and to advance the system at a stretch until the time of the event.

Abstract translation: 要解决的问题：通过预测ISS的输出定时和来自对应于输出定时的外设的输入定时来提高模拟速度。 解决方案：分析ISS216的程序代码，并为每个程序计数器估计I / O指令到达预测时间，并以第一级当时要输出的I / O指令的类型进行记录 表206.调度器被配置为经由ISS绘制具有其执行的程序计数器的值的第一级表，以获取I / O指令到达预测时间的信息和要输出的I / O指令 时间。 此外，调度器被配置为响应于从外围设备获取最快事件时间的I / O指令绘制第二级表212。 调度器被配置为通过使用这些信息来了解植物模拟器，外围模拟器和ISS中最近的将来发生的事件的时间，并且在一直到事件发生的时刻推进系统。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2009295126A

公开(公告)日：2009-12-17

申请号：JP2008151047

申请日：2008-06-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F19/00 ,  G06F11/28

CPC classification number: G06F17/5022 ,  G06F2217/86

Abstract: PROBLEM TO BE SOLVED: To increase processing speed in a simulation system, such as full vehicle SILS (Software In the Loop Simulation). SOLUTION: A physical device simulator is normally continuously performed speculatively at high speed and, only when an actual input enters, a speculative input is compared with the actual input. In response to it that they do not match, the physical device simulator is returned to a point of time nearest to a point of time of the actual input, and a variable step is performed to the point of time of the actual input. When the point of time of the actual input is reached, high-speed continuous performance is returned to, so that processing speed of the simulator is considerably increased. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提高仿真系统中的处理速度，例如全车SILS（软件在循环模拟中）。

解决方案：物理设备模拟器通常以高速推测连续执行，只有当实际输入进入时，将推测输入与实际输入进行比较。 响应于它们不匹配，物理设备模拟器返回到最接近实际输入时间点的时间点，并且在实际输入的时间点执行可变步长。 当达到实际输入的时间点时，返回高速连续性能，从而显着提高了模拟器的处理速度。 版权所有（C）2010，JPO＆INPIT