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    A SYSTEM FOR EMBEDDING AUTHENTICATION INFORMATION INTO AN IMAGE AND AN IMAGE ALTERATION DETECTING SYSTEM
    41.
    发明专利
    A SYSTEM FOR EMBEDDING AUTHENTICATION INFORMATION INTO AN IMAGE AND AN IMAGE ALTERATION DETECTING SYSTEM 未知

    公开(公告)号：CA2222346A1

    公开(公告)日：1998-05-28

    申请号：CA2222346

    申请日：1997-11-27

    Applicant: IBM

    Inventor： NUMAO MASAYUKI ,  SHIMIZU SHUICHI ,  MORIMOTO NORISHIGE

    IPC: H04N5/225 ,  G06T1/00 ,  H04N1/32 ,  H04N1/387 ,  H04N7/167 ,  H04N7/18 ,  H04N21/4405 ,  H04N21/4623 ,  H04N21/83 ,  H04L9/32 ,  H04N5/335

    Abstract: The invention provides a digital camera which embeds authentication informat ion for detecting the identity of a photographed image into the image. By supplying the authentication information integrally with image data, the verifier is enabl ed to verify the image data without saving the authentication information. By converting the light inputted through an optical system 21 to an electric signal, a CCD 22 outputs an anal og signal of an image. A signal processor 23 generates a digital signal of the image is r esponse to the analog signal. A digital camera has: a region dividing unit 24 for dividing the image into a first image region and a second image region in response to the digital si gnal; authentication information generator 29 for generating authentication inform ation from data in the first image region; encryptor 30 for encrypting the authentication in formation; hiding means 25 for embedding the encrypted authentication information into the sec ond image region by operating the data in the second image region; and region combinin g means 26 for combining the first image region in the image with the second image regi on in which the authentication information is embedded.

    Simulation execution method, program and system
    42.
    发明专利
    Simulation execution method, program and system 未知

    公开(公告)号：GB2508769A

    公开(公告)日：2014-06-11

    申请号：GB201405177

    申请日：2012-11-08

    Applicant: IBM

    Inventor： MURASE MASANA ,  ZHANG GANG ,  SHIMIZU SHUICHI

    IPC: G06F11/26

    Abstract: Provided is a technique which improves speed of parallel execution of logical processes without sacrificing accuracy of update timing of data in a parallel discrete event simulation method. The present invention is characterized in executing a logical process for which a longer time lag occurs for receiving than for transmitting for only an initial shift of a predetermined period of before starting an entire simulation. The initial shift is preferably set at half the value of the difference between the time lag for reception and the time lag for transmission. Logical processes which are shifted by only the initial shift of the predetermined period and executed operate by transmitting null messages to one another so that each of the null messages, after a predetermined time lag, arrives at a logical process of a peer, whereupon each of the logical processes further sends a null message to the logical process of the peer at the point when the first-mentioned null message has been received. In this manner, the simulation progresses by performing synchronization by way of the null messages.

    Simulationsverfahren, -system und -programm
    43.
    发明专利
    Simulationsverfahren, -system und -programm 未知

    公开(公告)号：DE112010004037T5

    公开(公告)日：2013-01-03

    申请号：DE112010004037

    申请日：2010-10-08

    Applicant: IBM

    Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOHICHI

    IPC: G06F11/28

    Abstract: Es wird eine V-PILS bereitgestellt, die es ermöglicht, die Reproduzierbarkeit eines Simulationsvorgangs zu erreichen und dabei eine sinnvolle Arbeitsgeschwindigkeit beizubehalten. Ein Peripherieeinheiten-Planer löscht die Beendigungsmerker aller Peripherieeinheiten-Emulatoren (setzt sie auf OFF (aus)), um dadurch deren parallelen Betrieb zu starten. Dann macht der Peripherieeinheiten-Planer auf der Grundlage der festgelegten Verarbeitungspausen-Zeitlage der einzelnen Peripherieeinheiten-Emulatoren einen der Peripherieeinheiten-Emulatoren ausfindig, für den am frühesten das Erreichen einer Verarbeitungspause geplant ist. Der gefundene Peripherieeinheiten-Emulator wird als Peripherieeinheit P bezeichnet. Im Falle, dass T eine Zeit der Verarbeitungspause der Peripherieeinheit P ist, fährt der Peripherieeinheiten-Planer mit der Ausführung von Prozessor-Emulatoren und Anlagensimulatoren bis zu einem Zeitpunkt der Zeit T fort. Der Peripherieeinheiten-Planer wartet auf das Setzen eines Beendigungsmerkers der Peripherieeinheit P. Als Reaktion auf das Setzen des Beendigungsmerkers der Peripherieeinheit P führt der Peripherieeinheiten-Planer eine Datensynchronisierung zwischen der Peripherieeinheit P, den Prozessor-Emulatoren und den Anlagensimulatoren durch.

    DATA HIDING METHOD AND SYSTEM USING STATISTICAL PROPERTIES
    45.
    发明专利
    DATA HIDING METHOD AND SYSTEM USING STATISTICAL PROPERTIES 未知

    公开(公告)号：MY117498A

    公开(公告)日：2004-07-31

    申请号：MYPI9705923

    申请日：1997-12-09

    Applicant: IBM

    Inventor： SHIMIZU SHUICHI

    IPC: G06F1/00 ,  G06F12/14 ,  G06F21/24 ,  G06T1/00 ,  G09C5/00 ,  G11B20/10 ,  H04N1/32 ,  H04N7/08 ,  H04N7/081

    Abstract: IT IS ENABLED TO EXTRACT EMBEDDED INFORMATION WITHOUT PROVIDING ORIGINAL MEDIA DATA AS INFORMATION, AND TO EXTRACT THE INFORMATION WITH RELATIVELY LOW CALCULATION COST.[CONSTITUTION] A DATA HIDING METHOD FOR EMBEDDING INFORMATION INDICATING A SPECIFIC MEANING INTO A MEDIA ARRAY EXPRESSING MEDIA DATA, THE MEDIA ARRAY COMPRISING A PLURALITY OF ARRAY ELEMENTS, THE METHOD COMPRISES THE STEPS OF: (A) PREPARING A PATTERN ARRAY HAVING A PLURALITY OF ARRAY ELEMENTS, THE PATTERN ARRAY HAVING AT LEAST A POSITIVE UNIT VALUE AND A NEGATIVE UNIT VALUE, AND THE SUM TOTAL OF THE POSITIVE AND NEGATIVE UNIT VALUES BEING ZERO; (B)SPECIFYING (N) NUMBER OF HIDING REGIONS IN THE MEDIA ARRAY, THE HIDING REGION HAVING A SIZE CORRESPONDING TO THAT OF THE PATTERN ARRAY; (C)DETERMINING AN AMOUNT OF OPERATION FOR EACH OF THE ARRAY ELEMENTS ACCORDING TO THE LOCATIONALLY CORRESPONDING POSITIVE OR NEGATIVE UNIT VALUE WITH RESPECT TO ONE OF THE HIDING REGIONS, BY REFERRING TO A HIDING RULE PROVIDING THE CORRESPONDENCE BETWEEN THE MEANING OF INFORMATION AND AN APPLICATION OF THE PATTERN ARRAY TO THE HIDING REGION; (D)ADDING THE DETERMINED AMOUNT OF OPERATION TO EACH OF THE ARRAY ELEMENTS WITH RESPECT TO THE HIDING REGION; AND (E)PERFORMING THE STEPS (C) TO (D) WITH RESPECT TO THE (N) NUMBER OF THE HIDING REGIONS SO THAT INFORMATION IS EMBEDDED INTO (N) NUMBER OF THE HIDING REGIONS. FIGURE 7

    Motion picture electronic watermark system
    48.
    发明专利
    Motion picture electronic watermark system 未知

    公开(公告)号：GB2349536B

    公开(公告)日：2003-03-12

    申请号：GB0003543

    申请日：2000-02-17

    Applicant: IBM

    Inventor： SHIMIZU SHUICHI ,  KOIDE AKIO

    IPC: H04N7/08 ,  G06T1/00 ,  H04N7/26 ,  H04N1/32

    Abstract: To provide an electronic watermark method and system for which the detection reliability of embedded information does not depend on the strength of signals that are measured in frames. To achieve the above object, information is prepared for embedding as a bit stream, the sign of the bit stream being changed in accordance with a sign inversion cycle, and the bit stream being embedded in a frame. As for detection of information, values obtained through observation of frames are accumulated, and the accumulated values are compared with threshold values that are varied in accordance with the accumulated values obtained by observation. The comparison results are then employed to detect the embedded information.

    DATA HIDING METHOD AND SYSTEM USING STATISTICAL PROPERTIES
    49.
    发明专利
    DATA HIDING METHOD AND SYSTEM USING STATISTICAL PROPERTIES 未知

    公开(公告)号：CA2222348C

    公开(公告)日：2002-10-29

    申请号：CA2222348

    申请日：1997-11-27

    Applicant: IBM

    Inventor： SHIMIZU SHUICHI

    IPC: G06T1/00 ,  H04N1/32 ,  G06F12/14

    Abstract: The invention provides a method to extract embedded information without prov iding original media data as information, and to extract the information with rela tively low calculation cost. A data hiding method is provided for embedding informatio n indicating a specific meaning into a media array expressing media data. The media array includes a plurality of array elements. The method includes the steps of: (a) preparing a pattern array having a plurality of array elements, the pat tern array having at least a positive unit value and a negative unit value, and the sum total of the positive and negative unit values being zero; (b) specifying (N) number of hiding regions in the media array, the hiding region having a size corresponding to that of the pattern array; (c) determining an amount of operation for each of the array elements accor dingto the locationally corresponding positive or negati ve unit value with respect to one of the hiding regions, by referring to a hiding rule providing the correspondence b etween the meaning of information and an application of the pattern array to the hiding region; (d) adding the determined amount of operation to each of the array elements with respect to the hiding region; and (e) performing the steps (c) to (d) with respect to the (N) number of the h iding regionsso that information is embedded into (N) number of the hiding regions .

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