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公开(公告)号：DE2855946A1
公开(公告)日：1979-07-05
申请号：DE2855946
申请日：1978-12-23
Applicant: IBM
Inventor： GRICE DONALD GEORGE , JOHNSON DAVID FREDERICK , WEINBERGER ARNOLD
Abstract: This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1....An-1 and B0, B1....Bn-1 plus a carry Cin. The decoders generate an output signal called a min term on a different line for each of the four possible combinations AiBi, AiBi, AiBi and AiBi of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms FP=F0(A0,B0) f1(A1,B1)....fn-1(An-1, Bn-1) fn(Cin) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit Si that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
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公开(公告)号：AU2259477A
公开(公告)日：1978-08-31
申请号：AU2259477
申请日：1977-02-23
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: Disclosed is a decoder which receives a number of coded binary-weighted input signals and which provides, on a plurality of output signal lines, a threshold related to the coded value of the input signals. The threshold is defined at the output as a consecutive sequence of output signal lines having a binary 0 value on one side of the threshold, and a consecutive sequence of output signals on the other side of the threshold having a binary value of 1. In one embodiment, a single level of binary logic receives n input signals and produces a threshold on m = 2n-1 output signal lines. A second embodiment receives n input signals which are divided into groups of signals, each group of which is applied to an intermediate threshold generator, the outputs of which are combined in a final level to provide m output signals. A further embodiment of the threshold decoder receives two groups of input signals which are combined in a first level of intermediate threshold generators, the outputs of which are then combined in a final stage which may produce more than one threshold on the output signal lines. Another further embodiment of the threshold decoder discloses a plurality of groups of input signal lines, combined in a plurality of intermediate threshold generators, the outputs of which are combined in a final level of logic to produce, selectively, a like plurality of thresholds on the output signal lines.
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公开(公告)号：FR2377063A1
公开(公告)日：1978-08-04
申请号：FR7737955
申请日：1977-12-09
Applicant: IBM
Inventor： LEVINE SAMUEL R , SINGH SHANKER , WEINBERGER ARNOLD
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Patent Agency Ranking
公开(公告)号：DE2556273A1
公开(公告)日：1976-07-08
申请号：DE2556273
申请日：1975-12-13
Applicant: IBM
Inventor： WEINBERGER ARNOLD
IPC: G11C17/00 , H03K17/00 , H03K19/177 , H03K19/00 , G06F7/38
Abstract: This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.
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公开(公告)号：FR2276656A1
公开(公告)日：1976-01-23
申请号：FR7516540
申请日：1975-05-21
Applicant: IBM
Inventor： MESSINA BENEDICTO U , WEINBERGER ARNOLD
Abstract: 1468783 Digital data storage systems INTERNATIONAL BUSINESS MACHINES CORP 4 April 1975 [27 June 1974] 13815/75 Heading G4A A memory system in which the number and sizes of memory hardware modules 12 are variable includes means for applying at least part of a word address 10 to each module present, and writable control means 14 responsive to some of the bits of the address to apply to the modules access-enabling signals generated as a function of said bits and of the current contents of the control means whereby module addressing can be adjusted by rewriting the writable control means. As disclosed, ten bits of the address go to the writable control means, and to each module goes a subset of these bits together with the remaining bits of the address and a select output from the writable control means. The writable control means has a notional matrix of stored bits, having 64 columns and 32 rows. Five bits of the address are decoded to select 1 of 32 columns, and five more address bits are decoded to select 1 of the other 32 columns. This reads out 2 bits for each row, these two bits being ORed together to form a row signal which, if O, selects a corresponding one of the memory modules mentioned. Some row signals may not be in use (depending on the number of modules), and two row signals may be ANDed together. The 32 x 64 bit notional matrix may be formed of 4 chips, each storing 16 x 32 bits and having its own decoder. The correspondence between addresses received and locations in the set of memory modules depends on the bit values stored in the writable control means 32 x 64 bit notional matrix. Selection of a given module may be prevented completely by loading all 1 bits into one half of the corresponding row. If part of a row is defective, its use in selection can be prevented by loading all 1 bits into the good half of the row. For added reliability, the same information may be stored in two rows and both used to select the corresponding module. To change the information stored in the 32 x 64 bit notional matrix, a 6-bit address is used to select a column and a 5-bit address is used to select a row. One bit from each of these addresses are combined to select one of the 4 chips, and the other 5 bits of the column address select a column within the chip, this column being read-out, and then re-written after a new bit value has been supplied to a bit position in the column selected by the other 4 bits of the row address. Thus the information is changed a bit at a time, selection being row by row. The stored information can also be read-out similarly without rewriting.
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公开(公告)号：DE1524898A1
公开(公告)日：1972-04-06
申请号：DE1524898
申请日：1967-12-27
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: 1,156,380. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 15 Dec., 1967 [28 Dec., 1966], No. 57205/67. Addition to 1,154,458. Heading G4C. In a memory system, a plurality of storage modules each store a bit of a word and each module has a plurality of drive lines and a plurality of sense lines to permit the concurrent accessing of data words, no two adjacent bits along any one of the drive lines being associated with the same sense line. An n-bit word is stored in n memory modules, one bit in each module (3D core matrix) in corresponding positions. Up to four words can be transferred simultaneously (read or write) between the modules and a data register, the words being adjacent in either the X, Y or Z direction. A system address specifies the X, Y and Z components of the bit address of the first word (in binary code), the direction referred to (direction of access). and the number of words. In the case of an X (or Y) direction access, up to four Y (or X) drivers (depending on the number of words required) and one X (or Y) driver are gated to the appropriate read-write lines in a plane of each module for coincident selection, under control of the X and Y components of the address of the first word, the plane involved in each module being selected by the Z component of the address of the first word. In the case of a Z direction access, one X and one Y driver are gated to the appropriate read-write lines (selected by the X and Y components) of up to four adjacent planes in each module (according to the Z component and the number of words). (As a modification, coincident selection may occur along those two of X, Y, Z unequal to the access direction). Each module uses four sense wires (each bit position being threaded by only one), the four wires threading each plane diagonally (a plurality of times) in turn, the threadings in each plane being sideways displaced by one position relative to those of the preceding plane. The four (or etc.) bits from each module on read-out are rotated to a standard position before entering the data register by gates controlled by the two low order bits of the sum of the X, Y and Z components of the first word address. Each core plane in the modules could be replaced by a plane of solid-state flip-flops using integrated or monolithic circuit technology, or each module could be a 1D or 2D core array or a plurality of 3D arrays, or thin-film storage could be used. Use in multiprocessor computers is mentioned.
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