公开(公告)号：DE102005031394A1

公开(公告)日：2007-01-18

申请号：DE102005031394

申请日：2005-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: H01L27/24

Abstract: A method for a resistive switching, especially phase change, memory cell comprises producing an electrode (10), depositing a phase change layer (11) with a switch active material comprising a gallium germanium indium antimonide compound and producing a second electrode (13). The phase change layer is doped with nitrogen or oxygen (12). An independent claim is also included for a phase change memory as above.

公开(公告)号：DE102005055651A1

公开(公告)日：2006-07-20

申请号：DE102005055651

申请日：2005-11-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  ZAIDI SHOAIB HASAN

IPC: G11C13/00

Abstract: A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for the plurality of phase-change memory cells with the temperature sensed by the temperature sensor.

公开(公告)号：DE102004031742A1

公开(公告)日：2006-01-19

申请号：DE102004031742

申请日：2004-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: H01L21/768 ,  H01L21/822 ,  H01L27/24

Abstract: Production of a sub-lithographic contact structure of a memory cell in a semiconductor component comprises preparing a front-end-of-line semiconductor wafer with an electrical contact (11), depositing an insulating layer (12) on the wafer, depositing a sacrificial layer on the insulating layer, forming an etching mask on the sacrificial layer, forming a first through hole in the sacrificial layer above the electrical contact, forming a second through hole in the insulating layer, removing the sacrificial layer, depositing a layer of resistance changing material on the insulating layer, and depositing and structuring an electrically conducting layer to form a contact electrode (20).

公开(公告)号：DE102004031135A1

公开(公告)日：2006-01-19

申请号：DE102004031135

申请日：2004-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: G11C13/02 ,  H01L21/76 ,  H01L21/822 ,  H01L27/24 ,  H01L29/04 ,  H01L45/00

Abstract: A nonvolatile, resistively switching memory cell has a layer of a porous dielectric between a first electrode. The dielectric is not a chalcogenide.

公开(公告)号：DE102004022604A1

公开(公告)日：2005-12-08

申请号：DE102004022604

申请日：2004-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: H01L21/283 ,  H01L27/24 ,  H01L45/00

Abstract: A process for producing a sublithographic contact structure in a semiconductor element, comprises forming primary and secondary electrical contacts (12,17), and providing one of the contact regions (26,28) with sublithographic dimensions. The dimensions are achieved by a chemical reaction during which at least one of the contact elements is turned into a dielectric.

公开(公告)号：DE102004015928A1

公开(公告)日：2005-10-27

申请号：DE102004015928

申请日：2004-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  HAPP THOMAS

IPC: G11C11/34 ,  G11C13/02 ,  G11C16/02 ,  G11C16/34

Abstract: The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

公开(公告)号：DE102004014965A1

公开(公告)日：2005-10-27

申请号：DE102004014965

申请日：2004-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: G11C16/00 ,  H01L21/8239 ,  H01L45/00

Abstract: A geometrical shape used for building in a fundamental rule to activate a solid-state electrolyte (16) produces a geometrical shape/structure for a memory element (11) and/or for an activated area in the solid-state electrolyte.

公开(公告)号：DE102004020575B3

公开(公告)日：2005-08-25

申请号：DE102004020575

申请日：2004-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  SYMANCZYK RALF

IPC: G11C11/00 ,  G11C13/02 ,  G11C16/02 ,  H01L27/24

Abstract: Parallel bit lines (1) of the programmable metallization memory cells lie at right angles to parallel word lines (2). Memory cells are located at the crossing points between the lines. Each memory zone (3) so defined, contains a chalcogenide glass presenting a pn junction to the bit line. Between the memory zone and the word line an electrode (4) forms a metallization memory cell.

公开(公告)号：DE102004053602A1

公开(公告)日：2005-06-30

申请号：DE102004053602

申请日：2004-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  KUND MICHAEL ,  SYMANCZYK RALF

IPC: G06F13/16 ,  G06F13/28 ,  G11C7/00 ,  G11C7/10 ,  G11C16/00

Abstract: According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: Sending out a signal to select one of several possible modes for the memory component; and Operating the memory component in accordance with the specific mode selected by the signal.