公开(公告)号：JP2001189354A

公开(公告)日：2001-07-10

申请号：JP2000334568

申请日：2000-11-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL

IPC: G01R1/06 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/66 ,  H01L41/09

Abstract: PROBLEM TO BE SOLVED: To adjust a needle card adjusting device for flattening, in relation to a wafer 8 to be contactedly formed with the needle set 6 of a needle card 1, connected with a substrate 3 which is used as a contact interface to an inspection head 5, more simply. SOLUTION: A needle card is connected with a substrate 3 via adjusting units 4 and 11, which are actuated separately and dynamically.

公开(公告)号：WO2005010983A2

公开(公告)日：2005-02-03

申请号：PCT/DE2004001588

申请日：2004-07-21

Applicant: INFINEON TECHNOLOGIES AG ,  KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

Inventor： KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8247

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C13/0014 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention concerns a method for producing a memory cell (1) comprising an organic storage layer (10), storing a digital information. Said method consists in carrying out a treatment of polycrystalline and monocrystalline semiconductor structures, during which said structures are subjected to high temperatures prior to applying the organic storage layer (10).

Abstract translation: 当生产具有数字信息存储有机存储层（10）的存储单元（1）之前，将有机存储层（10）完成的多晶和单晶半导体结构的处理可以被应用到高的温度。

公开(公告)号：DE10350168A1

公开(公告)日：2005-06-16

申请号：DE10350168

申请日：2003-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL

IPC: G11C7/24 ,  G11C11/406 ,  G11C16/34

Abstract: A memory arrangement and method of operating a memory arrangement is disclosed. In one embodiment of the memory arrangement according to the invention, rewritable memory cells are arranged at crossovers between word lines and bit lines, said memory cells being configured in such a manner that the information stored in them is essentially read out in a nondestructive manner. According to the invention, the memory arrangement has a flag cell either for each word line or for each bit line, said flag cell being able to store an item of information that indicates whether at least one of the memory cells either along the respective word line or along the respective bit line has been subjected to a reading operation since a basic state occurred.

公开(公告)号：DE10333557A1

公开(公告)日：2005-02-24

申请号：DE10333557

申请日：2003-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8247 ,  H01L21/8239 ,  H01L51/20

Abstract: When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.

公开(公告)号：DE10127656A1

公开(公告)日：2003-01-09

申请号：DE10127656

申请日：2001-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  KEIM MARTIN

IPC: G01R31/3193

Abstract: The device supplies to the circuit (12) a test signal that comprises a signal edge occurring at a reference time point. The output of the circuit is sampled at predetermined time points to obtain a sequence of samples. Signal values are associated with 'pass' and 'fail' states. The number of samples that are associated with a 'pass' state are counted and used to determine the delay time. Independent claims are also included for: (1) a method of detecting delay time; (2) an apparatus for detecting a change in the length of an input test pulse.

公开(公告)号：DE10056546C1

公开(公告)日：2002-06-20

申请号：DE10056546

申请日：2000-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  SALCHNER REINHARD

IPC: G11C11/22 ,  G11C7/24

Abstract: A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the imprint effect for increasing the remanent polarization or remanent magnetization of a material having a hysteresis property. The remanent polarization or magnetization is increased by writing a memory content a number of times to the same memory cells.

公开(公告)号：DE19952947A1

公开(公告)日：2001-05-23

申请号：DE19952947

申请日：1999-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  OSTENDORF HANS-CHRISTOPH

IPC: G06F11/00 ,  G11C7/10 ,  G11C7/00 ,  G11C29/00

Abstract: The read out device provides parallel read out of the register information held in a semiconductor chip using 2 or more input/output paths (I/O1,I/O2,...I/On), respectively associated with memory banks of the semiconductor chip via an input/output gating stage (2). The information is read out from the register, in which it is stored in the form of a number of fuses, via a multiplexer (4) operated in a test mode and line and column decoders (3,5) and entered in the memory banks via the input/output gating stage.

公开(公告)号：DE102008014295B4

公开(公告)日：2017-09-14

申请号：DE102008014295

申请日：2008-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  PACHA CHRISTIAN ,  SCHOENAUER TIM

IPC: G11C16/02 ,  H01L27/10

Abstract: Speichervorrichtung, umfassend: einen Multi-Gate-Feldeffekttransistor (115) mit einer Finne (120; 420; 500; 600; 700; 800) mit einem Kontaktbereich (510; 610; 715, 820); und ein programmierbares Speicherelement (110; 425; 515; 615), welches an den Finnenkontaktbereich (510; 610; 715, 820) stößt, wobei das programmierbare Speicherelement (110; 425; 515; 615) einen resistiven Speicher umfasst, wobei der Kontaktbereich (510) kleiner als ein Bereich eines programmierbaren Volumenabschnitts des resistiven Speicherelements (515) ist, an welchen er stößt, wobei die Finne (120; 420; 500; 600; 700; 800) und das resistive Speicherelement (110) von einem Substrat (124) getragen werden und das resistive Speicherelement (110) seitlich zu der Finne (120; 420; 500; 600; 700; 800) auf dem Substrat (124) angeordnet ist.

公开(公告)号：DE102005037286A1

公开(公告)日：2007-02-08

申请号：DE102005037286

申请日：2005-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL ,  WILLER JOSEF

IPC: H01L27/115 ,  G11C16/02

Abstract: The channel regions (T) of the memory cells are directed transversly to the word lines ( 2 ), which are arranged parallel at a distance from one another. Local interconnects ( 6 ) connect the source/drain regions of the memory cell transistors to bit lines running across the word lines and are connected to local interconnects in every next but one interspace between neighboring word lines. Every local interconnect is connected to only one source/drain region, which is enabled by enlarged shallow trench isolations ( 7 ) between the active areas. This memory cell array allows an individual programming and erasing of every single cell and can be integrated with a flash memory array comprising local interconnects and upper bit lines and is intended for file storage.

公开(公告)号：DE102005024897A1

公开(公告)日：2006-12-07

申请号：DE102005024897

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD JOERG ,  SCHOENAUER TIM ,  KUND MICHAEL ,  KAMP WINFRIED ,  DRAXELMAYR DIETER

IPC: G11C13/00 ,  G11C16/02

Abstract: The memory cell (500) has two transistors (501, 502) whose source and drain connections are, respectively, coupled with nodes (503, 504). Transistors (509, 510) reduce leakage currents, which flow through non-volatile programmable resistors (507, 508), respectively. Source or drain connections of the resistors are coupled with connectors of the resistors or with connectors of the transistor (501, 502), respectively. An independent claim is also included for a semiconductor device with a non-volatile memory cell.