公开(公告)号：JP2006303460A

公开(公告)日：2006-11-02

申请号：JP2006072252

申请日：2006-03-16

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： PINNOW CAY-UWE

IPC: H01L27/10 ,  H01L45/00 ,  H01L49/00

CPC classification number: G11C13/0011 ,  G11C2213/79 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/1641 ,  H01L45/1658 ,  H01L45/1683 ,  Y10T29/41

Abstract: PROBLEM TO BE SOLVED: To provide an improved solid eletrolyte memory element which can increase the switching speed, and a method for manufacturing the solid electrolyte memory element. SOLUTION: The solid electrolite memory element is provided with an insoluble cathode electrode 210, an eluting anode electrode 240, and a solid electrolyte layer 230 having a defective portion between the above insoluble cathode electrode 210 and the eluting anode electrode 240, wherein its method for manufacturing the solid electrolyte memory element includes a process to form the desired defective portion in the above solid electrolyte matrix. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可提高开关速度的改进的固体电解质存储元件，以及制造固体电解质存储元件的方法。 解决方案：固体电解质存储元件设置有不溶性阴极电极210，洗脱阳极电极240和在上述不溶性阴极电极210和洗脱阳极电极240之间具有缺陷部分的固体电解质层230，其中 其制造固体电解质存储元件的方法包括在上述固体电解质基质中形成所需缺陷部分的工艺。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006222420A

公开(公告)日：2006-08-24

申请号：JP2006020767

申请日：2006-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  SYMANCZYK RALF

IPC: H01L27/10 ,  G11C13/00 ,  G11C13/02 ,  H01L49/00

Abstract: PROBLEM TO BE SOLVED: To provide an electric switching device in which electric switching-on is performed by a track (101) established in a switching device (100). SOLUTION: The switching device (100) comprises a first electrode unit (201), a second electrode unit (202), and an electrolyte layer (203) which is arranged between the first and second electrode units (201, 202) to be connected with these electrode units in contact. The track (101) is formed between the first and second electrode units (201, 202) through the electrolyte layer (203) by a conductive element (102) spreading inside the electrolyte layer (203) from the first electrode unit (201). A heating device (400) heats the switching device (100) during switching operation. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：WO2004077574A3

公开(公告)日：2004-11-18

申请号：PCT/DE2004000365

申请日：2004-02-27

Applicant: INFINEON TECHNOLOGIES AG ,  PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

Abstract: The invention relates to a semiconductor memory cell and a method for producing said cell. According to said method, the capacity (CFe) of a ferroelectric capacitor assembly, which is formed by the contact and/or a region of an essentially constant potential between the gate isolation region (GOX) and a ferroelectric region (16), the ferroelectric region (16) and an upper gate electrode (18), is configured in a reduced manner relative to conventional conditions and/or relative to the capacity (CGOX) of a gate insulation capacitor assembly, which is formed by the border surface between a channel region (K) and the gate insulation region (GOX), the gate insulation region (GOX) and the contact and/or the region of an essentially constant potential between the gate isolation region (GOX) and the ferroelectric region (16).

Abstract translation: 已提出了用于制备半导体存储器单元和方法，其中该电容由所述接触和/或一个Gateisolatiosbereich（GOX）之间实质上恒定电位的区域上形成的强电介质电容器布置的（CFE）和Ferroelektrikumsbereich（16 ），（该Ferroelektrikumsbereich 16）和上栅电极（18），相对于传统的条件和/或容量（相对CGOX）的栅极绝缘电容器布置，这是一个沟道区之间形成（从界面K）和栅极绝缘区（GOX）， 栅极绝缘区（GOX）和所述接触和/或Gateisolatiosbereich（GOX）和Ferroelektrikumsbereich（16）之间的大致恒定的电势的区域形成或减少。

公开(公告)号：WO2005010983A2

公开(公告)日：2005-02-03

申请号：PCT/DE2004001588

申请日：2004-07-21

Applicant: INFINEON TECHNOLOGIES AG ,  KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

Inventor： KUND MICHAEL ,  MIKOLAJICK THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L21/8247

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C13/0014 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention concerns a method for producing a memory cell (1) comprising an organic storage layer (10), storing a digital information. Said method consists in carrying out a treatment of polycrystalline and monocrystalline semiconductor structures, during which said structures are subjected to high temperatures prior to applying the organic storage layer (10).

Abstract translation: 当生产具有数字信息存储有机存储层（10）的存储单元（1）之前，将有机存储层（10）完成的多晶和单晶半导体结构的处理可以被应用到高的温度。

公开(公告)号：WO2006094867A8

公开(公告)日：2006-11-09

申请号：PCT/EP2006050712

申请日：2006-02-07

Applicant: INFINEON TECHNOLOGIES AG ,  PINNOW CAY-UWE ,  UFERT KLAUS-DIETER

Inventor： PINNOW CAY-UWE ,  UFERT KLAUS-DIETER

IPC: H01L45/00 ,  G11C13/02 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: The object to develop a nonvolatile resistively switching memory system that can be manufactured on the basis of CMOS technology is solved by the present invention a method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for using in semiconductor memory devices, in particular resistively switching memory devices or components, the method comprising at least the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulfur containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy, wherein one component A of the chalcogenide compounds ASexSy is constituted by materials of the IV elements main group, e.g. Ge, Si or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Abstract translation: 开发可以基于CMOS技术制造的非易失性电阻切换存储器系统的目的通过本发明解决，该方法用于制造具有结合或沉积在其中用于半导体存储器件中的硫族化物材料的电解质材料层的方法， 所述方法至少包括以下步骤：制造半导体衬底;在半导体衬底上沉积二元硫属化物层;在含硫层上沉积含硫层;以及形成三元硫族化物层，所述三元硫属元素化物层包含在 至少两种不同的硫族化合物ASexSy，其中硫族化合物ASexSy的一种组分A由IV元素主族的材料构成，例如 Ge，Si或过渡金属，优选由Zn，Cd，Hg或其组合组成的组。

公开(公告)号：WO2004040647A9

公开(公告)日：2004-10-21

申请号：PCT/DE0303583

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  MIKOLAJICK THOMAS ,  MOERT MANFRED ,  PINNOW CAY-UWE

Inventor： MIKOLAJICK THOMAS ,  MOERT MANFRED ,  PINNOW CAY-UWE

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/02

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11507

Abstract: The invention relates to a ferroelectric memory cell, comprising a ferroelectric tunnel layer (FeTL) which forms the ferroelectric memory cell together with a first electrical conducting region (1) and a second electrical conducting region (2). The ferroelectric tunnel layer (FeTL) is arranged between the both electrical conducting regions (1, 2).

Abstract translation: 根据本发明的铁电存储器单元包括与第一导电区域（1），并与第二导电区域（2），所述铁电存储器单元一起形成铁电体层隧道（远东纺织）。 两个导电区域之间的强电介质隧道层（远东纺织）（1，2）。

公开(公告)号：DE102005012047A1

公开(公告)日：2006-09-28

申请号：DE102005012047

申请日：2005-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE

IPC: H01L27/24 ,  G11C13/02

Abstract: The method involves coating a first electrode with a solid-state electrolyte layer under purposeful defect formation in partial crystalline solid-state electrolyte matrix, and then forming a second electrode on the solid-state electrolyte layer. Particle or ion irradiation is performed for the purposeful defect formation in the solid-state electrolyte matrix. An independent claim is included for the solid-state electrolyte memory.

公开(公告)号：DE102004037450A1

公开(公告)日：2006-03-16

申请号：DE102004037450

申请日：2004-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: H01L29/68

Abstract: The invention relates to a method for operating a switching or amplifier device ( 11, 111 ), and to a switching or amplifier device ( 11, 111 ) comprising: an active material ( 13, 113 ) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts ( 12 a, 12 b, 12 c).

公开(公告)号：DE102004026111A1

公开(公告)日：2005-12-22

申请号：DE102004026111

申请日：2004-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  PINNOW CAY-UWE

IPC: G11C13/00 ,  H01L21/8239 ,  H01L27/24 ,  H01L45/00

Abstract: The method involves production of a solid electrolyte memory cell which has a memory section. The cell has a solid electrolyte material area (11) made up of a solid electrolyte material (11'). The area is activated by doping it with a dopant (12) and then the cell is irradiated with ions or ion beam (30) either partly or completely.

公开(公告)号：DE102004020297A1

公开(公告)日：2005-11-17

申请号：DE102004020297

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： UFERT KLAUS DIETER ,  PINNOW CAY-UWE

IPC: G11C13/02 ,  H01L21/336 ,  H01L21/8239 ,  H01L27/24 ,  H01L45/00

Abstract: The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.