Abstract:
PROBLEM TO BE SOLVED: To stabilize operation of a PMC memory cell using a CBRAM memory array. SOLUTION: The PMC memory cell includes a solid electrolyte which is adapted to selectively develop and eliminate a conductive path depending on an applied electric field. The PMC memory cell is programmed to change to a programmed state by applying programming voltage, and is erased to change to an erased state by applying erase voltage. Refresh voltage is applied to the PMC memory cell predetermined times to stabilize the programmed state of the PMC memory cell. While applying the refresh voltage, programming of the PMC memory cell in the erased state to the programmed state is prevented, and that, by applying the refresh voltage, stabilizing the programmed state of the PMC memory cell is performed. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide an electric switching device in which electric switching-on is performed by a track (101) established in a switching device (100). SOLUTION: The switching device (100) comprises a first electrode unit (201), a second electrode unit (202), and an electrolyte layer (203) which is arranged between the first and second electrode units (201, 202) to be connected with these electrode units in contact. The track (101) is formed between the first and second electrode units (201, 202) through the electrolyte layer (203) by a conductive element (102) spreading inside the electrolyte layer (203) from the first electrode unit (201). A heating device (400) heats the switching device (100) during switching operation. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
A conductive bridge RAM (CBRAM) comprises memory cells on a base of active solid electrolyte (13) of alterable resistance embedded between two electrodes (BE,TE) applying given electric fields to switch between high resistance OFF and low resistance ON states. Resistive material (10) is embedded between the electrodes parallel to the electrolyte. An independent claim is also included for a production process for the above.
Abstract:
In a process to manufacture a nano-storage component for storage of an electronic charge, a laminar substrate (101) is accorded a gate dielectric coating (102). Ions (104) are deposited at a predetermined depth within the dielectric layer by an ion beam (202). The resulting structure is heat treated, producing crystals within the dielectric material at the required depth.
Abstract:
A solid-state electrolyte memory cell comprises a memory region (S) between anode (A) and cathode (K) on an ion-conductive material (I) having regions of different and controllable variable conductance (G). A barrier layer (B) between the ion-conductive and cathode layers suppresses a short, low-resistance error or hard write condition.
Abstract:
The cell has a control switch arranged between a programmable solid electrolyte layer (3) and a write line. The control switch has a control input connected with a select line. The control switch has a delimitation unit to limit current flowing through the solid electrolyte layer to a given amount of electrical charge for a writing process. The solid electrolyte layer is connected with a potential source. An oxide layer is provided between a floating gate and the solid electrolyte layer. An independent claim is also included for a method for writing data into a memory cell.
Abstract:
Resistive memory element has resistive memory cell (1) brought in different on-states with different electrical resistances by different electrical currents. The memory element has two power supply lines (BL,WL) and a third power supply line (PL) connected with a reference potential. Independent claims are also included for the following: (A) Arrangement for memory elements; (B) Solid state memory; (C) Application of memory element; and (D) Method for switching of resistive memory element between its on-state and off-state.
Abstract:
Method for producing and integrating solid body electrolyte memory cells comprises depositing a lower electrode material (7) on a silicon substrate (6), structuring the lower electrode material to form lower electrode strips, producing a layer stack on the electrode strips by depositing layers of a solid electrolyte material (4), a reactive material (9) and an upper electrode material (10), structuring the upper electrode material perpendicular to the electrode strips by etching the upper electrode material to produce upper electrode strips and structuring the remaining layer stack perpendicular to the lower electrode strips by etching the active layers, solid electrolyte material and reactive material to produce trenches (13) in the layer stack. An independent claim is also included for a system comprising a memory element with a solid electrolyte memory cell.
Abstract:
The invention relates to a chip card security device, a procedure to be used in securing a chip card, as well as a chip card ( 1 ), comprising: at least one memory component ( 11 ), which comprises an active material layer ( 13 ), in particular an active material layer ( 13 ) comprising a solid state electrolyte, which layer may be brought into more or less of a conductive state and/or a state exhibiting a higher or lower level of capacitance by means of appropriate switching procedures.