公开(公告)号：DE10156830B4

公开(公告)日：2005-05-12

申请号：DE10156830

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETER JOERG ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C17/18 ,  H01L23/525

公开(公告)号：DE19843470B4

公开(公告)日：2005-03-10

申请号：DE19843470

申请日：1998-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00

公开(公告)号：DE50104255D1

公开(公告)日：2004-11-25

申请号：DE50104255

申请日：2001-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: A circuit configuration for driving a programmable link has a drive circuit for the selection and blowing of the fuse, and also a shift register, by which an activation signal can be fed to the drive circuit. In order to provide the data to be blown, in a preferred embodiment, a volatile memory cell may be provided. The present circuit configuration enables the blowing of fuses and thus repair of defective memory cells in mass memories even after encapsulation of a chip having the mass memory. Moreover, the shift register described effectively prevents impermissibly high currents from being able to occur as a result of simultaneous blowing of too many fuses.

公开(公告)号：DE50102500D1

公开(公告)日：2004-07-08

申请号：DE50102500

申请日：2001-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a signal present at the data input, and also a volatile memory, whose output is preferably directly connected to the data input of the drive circuit. A circuit configuration for particularly fast and simple programming of fuses, in particular electrically programmable fuses, is thereby specified.

公开(公告)号：DE10255427A1

公开(公告)日：2004-06-17

申请号：DE10255427

申请日：2002-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDOLF JUERGEN ,  SCHAMBERGER FLORIAN

IPC: H01L23/525 ,  H01L21/768

Abstract: The first conductive track (3) is deposited on substrate (1) and on vertical end face of the track is deposited dielectric layer (5). A second conductive track (6) is so applied as to form a junction with dielectric layer by an end face (4), thus forming antifuse structure .There are several possibilities of deposition of dielectric layer, i.e. isotropic deposition to cover edges of first conductive track, anisotropic deposition carried out transversely to substrate surface, and deposition of first conductive track to form junction with substrate surface. Preferably first track is located in first trough (2) of substrate. Independent claims are included for antifuse structure.

公开(公告)号：DE10102871C2

公开(公告)日：2003-03-06

申请号：DE10102871

申请日：2001-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C29/48 ,  G01R31/3187 ,  G11C29/00 ,  H04L7/00

公开(公告)号：DE10115614A1

公开(公告)日：2002-10-10

申请号：DE10115614

申请日：2001-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C5/14 ,  G11C29/12 ,  H01L23/58 ,  G11C29/00 ,  H01L21/66 ,  H01L23/525

Abstract: The method involves supplying the device with a lower current from a standby current generator (11) in standby mode and from a normal current generator (12) in normal mode. The device is supplied by the standby generator in a test mode during a product development phase. The semiconducting component is supplied by the normal current generator in the production development phase alternatively or additionally to the standby current generator. AN Independent claim is also included for the following: a semiconducting memory component.

公开(公告)号：DE59901516D1

公开(公告)日：2002-06-27

申请号：DE59901516

申请日：1999-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C29/44 ,  G06F11/20 ,  G11C29/00

Abstract: The memory cells of an integrated memory are successively tested and immediately following the detection of a defect of the memory cell currently being tested, the affected row line or column line is replaced by programming one of the redundant lines. After a certain number of the redundant lines have been programmed, the programming of at least one of the redundant lines is canceled if a further defect is found. This redundant line is programmed for repairing a defect of another memory cell.

公开(公告)号：DE10063683A1

公开(公告)日：2002-03-14

申请号：DE10063683

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

IPC: G11C17/18 ,  G11C29/00 ,  G11C14/00 ,  H01L23/525

Abstract: The circuit has a programmable connection that outputs an actual signal (E) depending on a current conducting state. A demand signal (D) can be taken from the output of a demand value memory (9) depending on a demand conducting state of the programmed connection and an evaluation circuit (26) receives the demand and actual signals and outputs an indicator signal (F) to indicate a deviation between the demand and actual measurement states.

公开(公告)号：DE10026737A1

公开(公告)日：2001-12-13

申请号：DE10026737

申请日：2000-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00 ,  H01L21/66 ,  H01L25/10

Abstract: The method involves applying a chip select signal to the data line or DQ line of one semiconductor module from several semiconductor modules (21-28). The address of incorrect memory cell is applied to all the modules at the same time, and the module corresponded to that address and being chosen by selection signal, is repaired.