公开(公告)号：JP2000243925A

公开(公告)日：2000-09-08

申请号：JP2000038348

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  KAISER ROBERT ,  SCHNEIDER HELMUT

IPC: H01L27/10 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To supply power required for activating a memory cell field immediately with simple structure via a short power feed line by setting a first electrical connection line to a high ohmic state and a second electrical connection line to a low ohmic state. SOLUTION: A semiconductor integrated memory device consists of memory cell fields 1-8, and the cell fields 1-8 are arranged in a line and are interconnected via power feed lines 11 and 12 with low ohmic at both sides. Also, a power feed line 13 with low ohmic is connected to the surrounding of each of memory cell fields 1-8. Then, a sense amplifier 5 exists at regions among the memory cell fields 1-8. The power feed lines 11, 12, and 13 with low ohmic form a low-ohmic power supply circuit network, and the circuit network is connected to a power supply generator 9 via a high-ohmic line 10.

公开(公告)号：JP2001257568A

公开(公告)日：2001-09-21

申请号：JP2001031274

申请日：2001-02-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  KRASSER HANS-JURGEN ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H03K5/13 ,  H03K5/131 ,  H03K5/133

Abstract: PROBLEM TO BE SOLVED: To provide a simply structured device capable of forming a signal pulse having a prescribed pulse length by a module itself by improving the device. SOLUTION: A variable delay element consists of the serial circuit of an inverter, and a signal section free from delay for writing to each register and a signal section free from delay for reading from the register are arranged in parallel in this inverter.

公开(公告)号：JP2003036698A

公开(公告)日：2003-02-07

申请号：JP2002118452

申请日：2002-04-19

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

CPC classification number: G11C29/40

Abstract: PROBLEM TO BE SOLVED: To realize a method for a self-test of constitution elements of a semiconductor memory.
SOLUTION: This invention relates to a method for testing constitution elements of a semiconductor memory. Data is accumulated in a bank having matrix structure, and the matrix structure is provided with rows and columns to which addresses can be specified. In this method, an error address is transmitted for an external test layer in a compressed form from an error position in a bank. Rows or columns are divided into regions, error caused in each region are counted for each row or column, the number of errors in each region are compared with a threshold value for each row or column, and the comparison result is transmitted to a test device with an error address as additional information for each row or column.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：实现半导体存储器的构成元件的自检的方法。 解决方案：本发明涉及一种用于测试半导体存储器的构成元件的方法。 数据被存储在具有矩阵结构的存储体中，并且矩阵结构被提供有可以指定地址的行和列。 在该方法中，从银行的错误位置以压缩形式发送用于外部测试层的错误地址。 将行或列划分为区域，对每个行或列计数每个区域中引起的错误，将每个区域中的错误数与每行或列的阈值进行比较，并将比较结果发送到测试设备 将错误地址作为每行或列的附加信息。

公开(公告)号：JP2002198442A

公开(公告)日：2002-07-12

申请号：JP2001340062

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KAISER ROBERT ,  PFEFFERL KARL-PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/50 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory block having a flexible structure. SOLUTION: The memory structure has a contact block (1), and cell blocks (2-9) adjacent to the contact block (1). The contact block (1) is located in the center, the cell blocks (2-9) abut on the four sides of the contact block (1), respectively, and the cell blocks (2-9) are arranged annularly around the contact block (1). The cell block (2) has two sides abutting, respectively, on two other cell blocks (3, 9) and the cell blocks (2-9) are divided into first and second sub-cell blocks (21, 22) in the longitudinal direction.

公开(公告)号：JP2001243775A

公开(公告)日：2001-09-07

申请号：JP2001027358

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET ,  KAISER ROBERT

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To minimize a required area for a circuit device and to increase comparatively switching speed of a signal characteristics of a data signal to be read out, in a semiconductor integrated memory having the circuit device reading out the data signal. SOLUTION: This memory has memory cells storing the data signal, a sense amplifier, a driver circuit connected to an output side of the sense amplifier, a signal line path connected to an output side of the driver circuit, a pre-charge circuit connected to this signal line path, a memory circuit connected to the signal line path, and a control signal terminal connected to the sense amplifier, the pre-charge circuit, and the memory circuit, and the driver circuit can be activated or can be deactivated by only the output signal of the sense amplifier.

公开(公告)号：JP2000339988A

公开(公告)日：2000-12-08

申请号：JP2000138714

申请日：2000-05-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/04 ,  G11C7/10 ,  G11C8/06 ,  G11C11/404 ,  G11C14/00 ,  G11C29/30 ,  G11C29/44 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit device that can read stored information while leaving the stored information as it is, furthermore, examines based on the information whether information that should have been originally assigned to a volatile storage element can be restored from the state of an assigned programmable element or not, and inspects the state of a storage. SOLUTION: The circuit device is equipped with one programmable element 2 and a storage 10 with a volatile storage element 1. In order to store the state of the programmable element, the programmable element 2 is connected to the volatile storage element 1 for each storage 10. Each storage 10 has at least one of output sides Q1 and Q2 for inspecting each state of the programmable element 2 and the volatile storage element 1. In the storage 10, at the time when the state of the programmable element 2 and the volatile storage element 1 is outputted via a selection circuit, an address can be individually specified. Information stored into the volatile storage element remains as it is saved.

公开(公告)号：JP2002056689A

公开(公告)日：2002-02-22

申请号：JP2001157853

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To prevent surely rapid deterioration process of fuse/anti-fuse and unexpected burnout of fuse/anti-fuse being never burned out hitherto in reading out fuse/anti-fuse of a semiconductor memory assembly such as especially a DRAM. SOLUTION: In reading out of fuse/anti-fuse, voltage Vb1h deciding a high potential of a bit line BL of a memory cell array 6 is used instead of internal voltage Vint being general hitherto. The voltage Vb1h is reduced for the internal voltage Vint, especially, it is preferable that voltage Vb1h is reduced by almost 20% to 30% for the internal voltage Vint.

公开(公告)号：JP2000339989A

公开(公告)日：2000-12-08

申请号：JP2000140404

申请日：2000-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C29/04 ,  G11C17/18 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To allow a programmable element to be programmed with a high voltage and allow an area of a circuit element of a readout circuit to be saved by connecting a second terminal of the programmable element, to which a first terminal of a protective circuit is connected, to an input side of the readout circuit and by limiting a voltage at the second terminal. SOLUTION: A terminal al of a protective circuit 1 is connected to a terminal AF of a programmable element F, while a terminal a2 is connected to a terminal EA on an input side of a readout circuit A. During a programming process of the programming element F, an electrical potential V1 has a positive burn- voltage value. When a switchable element is switched so as to be conducting, the programmable element F is transferred into a low ohm condition and an electrical potential at a node K increases to the burn-voltage value. At this time, an electrical potential at a node N does not increase to exceed a sum of an electrical potential V3 corresponding to a normal positive operating voltage and a forward voltage of a diode D.

公开(公告)号：WO0250841A3

公开(公告)日：2003-03-13

申请号：PCT/DE0104540

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES AG ,  KAISER ROBERT ,  SCHAMBERGER FLORIAN

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: The invention relates to a circuit arrangement for controlling a programmable connection (1), comprising a volatile memory cell (5), which is coupled to the fuse (1) for permanently memorising the data that is stored in the volatile memory (5) and a shift register (3), which permits data to be read from the volatile memory cell (5) and data to be written to the memory cell (5). To control several fuses (1), several shift registers (3) can be interconnected to form a shift register chain. Said shift register chain (3) enables the rapid reading from and writing to the volatile memory (4), using a circuit of low complexity.

Abstract translation: 本发明涉及一种电路装置，用于驱动一个可编程链路（1），包括连接到（1），其耦合在所述易失性存储器（5）存储的数据永久地存储所述熔丝的非易失性存储单元（5），以及一个移位寄存器（3 ），这使得能够从所述易失性存储单元（5）和写入数据的数据的读出到存储单元（5）。 在这种情况下，用于控制多个熔断器（1）的可以被连接以形成一个移位寄存器链多个移位寄存器（3）。 这个移位寄存器链（3）因此允许低电路复杂性快速写和从非易失性存储器（4）读出到/。

公开(公告)号：WO0250839A2

公开(公告)日：2002-06-27

申请号：PCT/DE0104787

申请日：2001-12-18

Applicant: INFINEON TECHNOLOGIES AG ,  KAISER ROBERT ,  SCHAMBERGER FLORIAN

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  G11C17/18 ,  G11C

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A circuit arrangement for triggering a programmable connection (1), for example a fuse, is disclosed, comprising a trigger circuit (2) for triggering the fuse (1), dependent upon a signal applied to the data input (11), and a volatile memory (4), the output of which is preferably directly connected to the data input (11) of the trigger circuit. A trigger circuit for the particularly rapid and simple programming of fuses, in particular electrical programmable fuses is thus disclosed.

Abstract translation: 用于驱动的​​可编程链路的电路装置（1），例如，熔丝，-任选地与控制电路（2），用于触发所述熔断器（1）响应于数据输入端（11）信号施加到以及一个 其输出（23）易失性存储器（4）优选地直接与驱动电路的数据输入（11）连接。 以这种方式，熔断器的一个特别快速和容易编程的电路装置，电可编程熔丝特别指示。