公开(公告)号：US11923312B2

公开(公告)日：2024-03-05

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Srinivas Pietambaram ,  Jesse Jones ,  Yosuke Kanaoka ,  Hongxia Feng ,  Dingying Xu ,  Rahul Manepalli ,  Sameer Paital ,  Kristof Darmawikarta ,  Yonggang Li ,  Meizi Jiao ,  Chong Zhang ,  Matthew Tingey ,  Jung Kyu Han ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US11088062B2

公开(公告)日：2021-08-10

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Dingying David Xu ,  Sheng C. Li ,  Matthew L. Tingey ,  Meizi Jiao ,  Chung Kwang Christopher Tan

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.