公开(公告)号：US20230060727A1

公开(公告)日：2023-03-02

申请号：US17412810

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Krishna Bharath ,  William J. Lambert ,  Adel A. Elsherbini ,  Sriram Srinivasan ,  Christopher Schaef

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

公开(公告)号：US20220406701A1

公开(公告)日：2022-12-22

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US20210098436A1

公开(公告)日：2021-04-01

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20200066627A1

公开(公告)日：2020-02-27

申请号：US16108953

申请日：2018-08-22

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02 ,  H01L23/64

Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

公开(公告)号：US20200003829A1

公开(公告)日：2020-01-02

申请号：US16020425

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： William Lambert ,  Kaladhar Radhakrishnan ,  Michael Hill

IPC: G01R31/28 ,  G05F1/46

Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.

公开(公告)号：US09753510B2

公开(公告)日：2017-09-05

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  G06F1/32 ,  H02J1/00 ,  H02M3/158 ,  H02M1/00

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

公开(公告)号：US20150155092A1

公开(公告)日：2015-06-04

申请号：US14616508

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Robert L. Sankman ,  Brent S. Stone ,  Kaladhar Radhakrishnan ,  Joshua D. Heppner

IPC: H01F27/28 ,  H01F27/06 ,  H01F27/02

CPC classification number: H01F27/2852 ,  H01F17/045 ,  H01F27/02 ,  H01F27/027 ,  H01F27/06 ,  H01F27/2847 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T29/4902 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有围绕芯设置的一个或多个导电材料条的电感器结构。 条带可以在条的第一端和第二端处具有触点，并且可以在接触件之间具有间隙而围绕芯设置。 电感器结构可以安装在衬底的表面上，并且可以在衬底的表面中形成一个或多个迹线，以将两个或更多个导电材料条彼此电耦合以形成感应线圈。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20250103075A1

公开(公告)日：2025-03-27

申请号：US18474156

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Nicolas Butzen ,  Nachiket Desai ,  Su Hwan Kim ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.

公开(公告)号：US20230097714A1

公开(公告)日：2023-03-30

申请号：US17485208

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

公开(公告)号：US20230095608A1

公开(公告)日：2023-03-30

申请号：US17485250

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Henning Braunisch ,  Thomas L. Sounart ,  Johanna Swan ,  Beomseok Choi ,  Krishna Bharath ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H05K3/14 ,  H05K3/10 ,  H05K3/30 ,  H01L21/768 ,  H01L21/82

Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.