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41.
公开(公告)号:US11070476B2
公开(公告)日:2021-07-20
申请号:US16395774
申请日:2019-04-26
Applicant: Intel Corporation
Inventor: Patrick Connor , Andrey Chilikin , Brendan Ryan , Chris MacNamara , John J. Browne , Krishnamurthy Jambur Sathyanarayana , Stephen Doyle , Tomasz Kantecki , Anthony Kelly , Ciara Loftus , Fiona Trahe
IPC: H04W56/00 , H04L12/803 , G06F9/455 , H04L12/851 , H04L12/26 , G06F8/76
Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
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公开(公告)号:US20200301864A1
公开(公告)日:2020-09-24
申请号:US16894437
申请日:2020-06-05
Applicant: INTEL CORPORATION
Inventor: Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
IPC: G06F13/40
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
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公开(公告)号:US10693781B2
公开(公告)日:2020-06-23
申请号:US14931179
申请日:2015-11-03
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Peter P. Waskiewicz, Jr. , Patrick Connor
IPC: H04L12/741 , H04L29/08 , H04L29/12 , H04L12/863 , H04L29/06
Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.
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44.
公开(公告)号:US20190052457A1
公开(公告)日:2019-02-14
申请号:US15941114
申请日:2018-03-30
Applicant: Intel Corporation
Inventor: Patrick Connor , Scott Dubal , Andrew J. Herdrich , James R. Hearn , Kapil Sood
Abstract: Technologies for providing efficient sharing of encrypted data in a disaggregated architecture include a sled. The sled includes a set of memory devices and a controller connected to the set of memory devices. The memory controller is to receive, from a first application executed by a compute sled, a data access request to share a data set between the first application and a second application. The data set is encrypted in one or more of the memory devices. Additionally, the controller is to determine, in response to the data access request, a key identifier that uniquely identifies a key that is usable to perform cryptographic operations on the data set. Further, the controller is to send, to an encryption key manager, a request to provide the key corresponding to the key identifier to be used by the second application to decrypt the data set and send, to the second application, a handle associated with an address in the set of memory devices where the data set is located.
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公开(公告)号:US20190044893A1
公开(公告)日:2019-02-07
申请号:US16024774
申请日:2018-06-30
Applicant: Intel Corporation
Inventor: Bruce Richardson , Chris MacNamara , Patrick Fleming , Tomasz Kantecki , Ciara Loftus , John J. Browne , Patrick Connor
IPC: H04L12/861 , H04L12/879
Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.
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公开(公告)号:US10063446B2
公开(公告)日:2018-08-28
申请号:US14751819
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Scott P. Dubal , James R. Hearn , Patrick Connor
CPC classification number: G06F9/45558 , G06F2009/45595 , H04L41/046 , H04L43/026 , H04L43/12 , H04L43/14
Abstract: Methods and apparatus for collection of Netflow data and export offload using network silicon. In accordance with aspects of the embodiments, the Netflow export and collection functions are offloaded to the network silicon in the chipset, System on a Chip (SoC), backplane switch, disaggregated switch, virtual switch (vSwitch) accelerator, and Network Interface Card/Controller (NIC) level. For apparatus implementing virtualized environments, one or both of the collection and export functions are implemented at the Physical Function (PF) and/or Virtual Function (VF) layers of the apparatus.
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公开(公告)号:US20180164868A1
公开(公告)日:2018-06-14
申请号:US15375756
申请日:2016-12-12
Applicant: Intel Corporation
Inventor: Brian J. Skerry , Ira Weiny , Patrick Connor , Tsung-Yuan C. Tai , Alexander W. Min
IPC: G06F1/32
CPC classification number: G06F1/3243 , G06F1/3209 , H04L49/40 , H04L49/70 , Y02D10/152
Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
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公开(公告)号:US09985886B2
公开(公告)日:2018-05-29
申请号:US14671776
申请日:2015-03-27
Applicant: Intel Corporation
Inventor: Jesse C. Brandeburg , Scott P. Dubal , Patrick Connor , David E. Cohen
IPC: H04L12/801 , H04L12/26 , H04L12/805
CPC classification number: H04L47/12 , H04L43/0864 , H04L47/36
Abstract: Technologies for pacing transmission of network packets by a computing device to a remote computing device include performing a segmentation offload operation to segment a payload of a network packet into a plurality of network packet segments in response to a determination that a size of the payload is greater than a maximum allowable payload size. The computing device additionally determines a packet pacing interval and transmits the plurality of network packet segments to the remote computing device at a transmission rate based on the packet pacing interval.
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49.
公开(公告)号:US20160380865A1
公开(公告)日:2016-12-29
申请号:US14751819
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Scott P. Dubal , James R. Hearn , Patrick Connor
CPC classification number: G06F9/45558 , G06F2009/45595 , H04L41/046 , H04L43/026 , H04L43/12 , H04L43/14
Abstract: Methods and apparatus for collection of Netflow data and export offload using network silicon. In accordance with aspects of the embodiments, the Netflow export and collection functions are offloaded to the network silicon in the chipset, System on a Chip (SoC), backplane switch, disaggregated switch, virtual switch (vSwitch) accelerator, and Network Interface Card/Controller (NIC) level. For apparatus implementing virtualized environments, one or both of the collection and export functions are implemented at the Physical Function (PF) and/or Virtual Function (VF) layers of the apparatus.
Abstract translation: 使用网络硅收集Netflow数据和出口卸载的方法和设备。 根据实施例的方面,Netflow导出和收集功能被卸载到芯片组,片上系统(SoC),背板交换机,分解交换机,虚拟交换机(vSwitch)加速器和网络接口卡/ 控制器(NIC)级别。 对于实施虚拟化环境的设备,收集和导出功能中的一个或两个在设备的物理功能(PF)和/或虚拟功能(VF)层上实现。
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公开(公告)号:US09471350B2
公开(公告)日:2016-10-18
申请号:US14037814
申请日:2013-09-26
Applicant: Intel Corporation
Inventor: Chris Pavlas , Duke C. Hong , Scott P. Dubal , Elizabeth M. Kappler , Patrick Connor , Matthew A. Jared
CPC classification number: G06F9/45533 , G06F9/45558 , G06F2009/4557 , G06Q10/06315
Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.
Abstract translation: 用于支持虚拟化系统迁移和缩放的方法,设备,软件和系统架构。 在方法的方面,数据被多个级别自动地收集和聚合,由多个代理针对多个数据中心中的每一个。 数据包括与虚拟机利用有关的数据,与电力利用成本有关的数据,与数据中心利用有关的数据以及与触发事件有关的数据。 处理数据以确定是否将虚拟服务器从第一个数据中心迁移到第二个数据中心。 软件架构包括多个模块,包括控制器,数据中心配置文件,转换触发器,电源成本配置文件和虚拟机包模块。 代理在代理层级中实现,并被配置为自己收集数据和/或从其他代理聚合数据,并提供API以便于访问收集的数据和代理服务。
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