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    Use of a single instruction set architecture (ISA) instruction for vector normalization
    41.
    发明授权
    Use of a single instruction set architecture (ISA) instruction for vector normalization 有权

    公开(公告)号：US11157238B2

    公开(公告)日：2021-10-26

    申请号：US16685561

    申请日：2019-11-15

    Applicant: Intel Corporation

    Inventor： Abhishek Rhisheekesan ,  Supratim Pal ,  Shashank Lakshminarayana ,  Subramaniam Maiyuran

    IPC: G06F7/552 ,  G06F9/30

    Abstract: Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.

    SPARSE MATRIX OPTIMIZATION MECHANISM
    42.
    发明申请
    SPARSE MATRIX OPTIMIZATION MECHANISM 有权

    公开(公告)号：US20210183002A1

    公开(公告)日：2021-06-17

    申请号：US16710081

    申请日：2019-12-11

    Applicant: Intel Corporation

    Inventor： Namita Sharma ,  Supratim Pal ,  Biju P. Simon ,  Tovinakere D. Vivek

    IPC: G06T1/20

    Abstract: An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.

    Instruction that performs a scatter write
    46.
    发明授权
    Instruction that performs a scatter write 有权

    公开(公告)号：US09880839B2

    公开(公告)日：2018-01-30

    申请号：US14261097

    申请日：2014-04-24

    Applicant: Intel Corporation

    Inventor： Wei-Yu Chen ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Supratim Pal

    IPC: G06F9/30

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline has an instruction fetch stage to fetch an instruction specifying multiple target resultant registers. The instruction execution pipeline has an instruction decode stage to decode the instruction. The instruction execution pipeline has a functional unit to prepare resultant content specific to each of the multiple target resultant registers. The instruction execution pipeline has a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.

    DYNAMIC THREAD SPLITTING
    47.
    发明申请
    DYNAMIC THREAD SPLITTING 审中-公开
    动态螺纹分割

    公开(公告)号：US20170010894A1

    公开(公告)日：2017-01-12

    申请号：US14794521

    申请日：2015-07-08

    Applicant: Intel Corporation

    Inventor： Hema C. Nalluri ,  Supratim Pal ,  Subramaniam Maiyuran ,  Joy Chandra

    IPC: G06F9/30

    Abstract: Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.

    Abstract translation: 系统，装置和方法可以提供将第一指令指针与与线程相关联的主IF-ELSE条件结构的IF块相关联，并且响应于与IF块相关联的依赖关系来激活第二指令指针。 另外，第二指令指针可以与主IF-ELSE条件构造的ELSE块相关联。 在一个示例中，IF块和ELSE块经由第一指令指针和第二指令指针执行独立于或彼此平行的一个或多个。

    SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
    48.
    发明申请
    SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH 有权

    公开(公告)号：US20250117360A1

    公开(公告)日：2025-04-10

    申请号：US18931412

    申请日：2024-10-30

    Applicant: Intel Corporation

    Inventor： Jorge Parra ,  Wei-yu Chen ,  Kaiyu Chen ,  Varghese George ,  Junjie Gu ,  Chandra Gurram ,  Guei-Yuan Lueh ,  Stephen Junkins ,  Subramaniam Maiyuran ,  Supratim Pal

    IPC: G06F15/80 ,  G06F9/30

    Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

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