公开(公告)号：US11387533B2

公开(公告)日：2022-07-12

申请号：US16032589

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Dirk Hammerschmidt ,  Walter Hartner ,  Johannes Lodermeyer ,  Chiara Mariotti ,  Thorsten Meyer

IPC: G02B6/12 ,  H01P3/16 ,  H01Q3/44 ,  H01L23/66

Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.

公开(公告)号：US11171066B2

公开(公告)日：2021-11-09

申请号：US16690963

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Andreas Grassmann

IPC: H01L23/055 ,  H01L21/48 ,  H01L21/52 ,  H01L23/08

Abstract: A method for manufacturing a semiconductor panel is disclosed. In one example, the method includes providing a first preformed polymer form. The method further includes arranging multiple semiconductor chips over the first preformed polymer form. The method further includes attaching a second preformed polymer form to the first preformed polymer form, wherein the semiconductor chips are arranged between the attached preformed polymer forms, and wherein the attached preformed polymer forms form the semiconductor panel encapsulating the semiconductor chips.

公开(公告)号：US10916484B2

公开(公告)日：2021-02-09

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US10707158B2

公开(公告)日：2020-07-07

申请号：US15497267

申请日：2017-04-26

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Bernd Goller ,  Thorsten Meyer ,  Gerald Ofner

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

公开(公告)号：US20190304858A1

公开(公告)日：2019-10-03

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/40 ,  H01L23/00 ,  H01L23/08

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US20180374769A1

公开(公告)日：2018-12-27

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US20150076591A1

公开(公告)日：2015-03-19

申请号：US14027683

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Werner Schwetlick

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823487 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches.

Abstract translation: 半导体器件包括具有第一表面和与第一表面相对的第二表面的半导体本体。 半导体器件还包括从第一表面延伸到半导体本体的第一和第二沟槽。 半导体器件还包括至少一个横向IGFET，其包括第一表面处的第一负载端子，第一表面处的第二负载端子和第一沟槽内的栅电极。 半导体器件还包括至少一个垂直IGFET，其包括第一表面处的第一负载端子，第二表面处的第二负载端子和第二沟槽内的栅电极。

公开(公告)号：US20140332885A1

公开(公告)日：2014-11-13

申请号：US14446741

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A lateral trench transistor has a semiconductor body having a source region, a source contact, a body region, a drain region, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded. A heavily doped semiconductor region is provided within the body region or adjacent to it, and is electrically connected to the source contact, and whose dopant type corresponds to that of the body region.

Abstract translation: 横向沟槽晶体管具有半导体本体，其具有嵌入与半导体本体隔离的栅电极的源极区，源极接触，体区，漏极区和栅极沟槽。 重掺杂半导体区域设置在体区内或与其相邻，并且与源极接触电连接，并且其掺杂剂类型对应于身体区域。

公开(公告)号：US12136670B2

公开(公告)日：2024-11-05

申请号：US17824198

申请日：2022-05-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L21/74 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.