公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US20230200119A1

公开(公告)日：2023-06-22

申请号：US17556768

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Kristof Darmawikarta

IPC: H01L51/52 ,  H01L51/56

CPC classification number: H01L51/5275 ,  H01L51/56 ,  H01L51/5237

Abstract: Disclosed herein are organic semiconductors using optical signaling on a microelectronics package and methods for manufacturing the same. The microelectronics packages may include a substrate, an acceptor, a donor, and a solder resist layer. The substrate may include a trace. The acceptor may be in electrical communication with the trace. The donor may be connected to the acceptor. The solder resist layer may be connected to the substrate and encapsulate a portion of at least the acceptor.

公开(公告)号：US20220406654A1

公开(公告)日：2022-12-22

申请号：US17351536

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Leonel R. Arana ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Brandon Christian Marin

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G03F7/00 ,  G03F7/16

Abstract: Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity and low-photosensitivity photoresist are applied to a substrate and exposed at the same time with use of a dual-tone mask. After being developed, one photoresist forms an overhang over a sheltered region. The mold formed by the photoresists is filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the sheltered region forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

公开(公告)号：US11081768B2

公开(公告)日：2021-08-03

申请号：US16421989

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jeremy D. Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Yonggang Li ,  Dilan Seneviratne

IPC: H01P1/208 ,  H01P1/20 ,  H01P7/10 ,  H01L23/66 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.

公开(公告)号：US20200312787A1

公开(公告)日：2020-10-01

申请号：US16369681

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Brandon C. Marin ,  Vahidreza Parichehreh ,  Jeremy D. Ecton

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

公开(公告)号：US20190304912A1

公开(公告)日：2019-10-03

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20180286700A1

公开(公告)日：2018-10-04

申请号：US15474302

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Changhua Liu ,  Arnab Roy ,  Oscar U. Ojeda ,  Timothy A. White ,  Nicholas S. Haehn

IPC: H01L21/3213 ,  H01L21/67

CPC classification number: H01L21/32134 ,  H01L21/32139 ,  H01L21/6708 ,  H05K3/067

Abstract: The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate. These anisotropic voids may be more closely spaced (i.e., arranged on a tighter pitch) than the isotropic voids produced using conventional etching technologies. By placing the voids in the semiconductor substrate on a tighter pitch, greater component density may be achieved.