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    CPU hot-swapping
    41.
    发明授权
    CPU hot-swapping 有权

    公开(公告)号：US11327918B2

    公开(公告)日：2022-05-10

    申请号：US17041519

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

    IPC: G06F13/40 ,  G06F9/4401 ,  G06F11/20

    Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

    Apparatus and method to identify the source of an interrupt
    42.
    发明授权
    Apparatus and method to identify the source of an interrupt 有权

    公开(公告)号：US11048512B1

    公开(公告)日：2021-06-29

    申请号：US16833598

    申请日：2020-03-28

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

    IPC: G06F9/50 ,  G06F9/30 ,  G06F15/80 ,  G06F9/48

    Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

    Delayed error processing
    43.
    发明授权
    Delayed error processing 有权

    公开(公告)号：US10929232B2

    公开(公告)日：2021-02-23

    申请号：US15610067

    申请日：2017-05-31

    Applicant: Intel Corporation

    Inventor： Subhankar Panda ,  Sarathy Jayakumar ,  Gaurav Porwal ,  Theodros Yigzaw

    IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G06F11/20

    Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

    DEPLOYMENT OF BIOS TO OPERATING SYSTEM DATA EXCHANGE
    44.
    发明申请
    DEPLOYMENT OF BIOS TO OPERATING SYSTEM DATA EXCHANGE 审中-公开

    公开(公告)号：US20200257541A1

    公开(公告)日：2020-08-13

    申请号：US16790203

    申请日：2020-02-13

    Applicant: Intel Corporation

    Inventor： Sarathy Jayakumar ,  Mohan Kumar

    IPC: G06F9/445 ,  G06F16/22 ,  G06F13/16

    Abstract: Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.

    Fast memory initialization
    50.
    发明申请
    Fast memory initialization 审中-公开

    公开(公告)号：US20170185486A1

    公开(公告)日：2017-06-29

    申请号：US14998196

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Mohan J. Kumar ,  George Vergis ,  Sarathy Jayakumar

    IPC: G06F11/14 ,  G06F11/30 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F13/16 ,  G06F13/28 ,  G06F21/14 ,  G06F21/53 ,  G06F2221/2143

    Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.

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