公开(公告)号：US20230146165A1

公开(公告)日：2023-05-11

申请号：US18091989

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Yonggang LI ,  Sameer PAITAL

IPC: H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64

CPC classification number: H01F27/26 ,  H01F27/425 ,  H01L21/76871 ,  H01L23/645 ,  H01F27/25

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US20220115334A1

公开(公告)日：2022-04-14

申请号：US17556667

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20210078296A1

公开(公告)日：2021-03-18

申请号：US16574252

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Patrick QUACH ,  Dilan SENEVIRATNE

IPC: B32B17/10 ,  B32B15/20 ,  H01L23/48 ,  H01L23/00

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20210028101A1

公开(公告)日：2021-01-28

申请号：US16522483

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Bai NIE ,  Haobo CHEN ,  Gang DUAN ,  Brandon C. MARIN ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material.

公开(公告)号：US20210005542A1

公开(公告)日：2021-01-07

申请号：US16502622

申请日：2019-07-03

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.

公开(公告)号：US20200312768A1

公开(公告)日：2020-10-01

申请号：US16366647

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Marcel WALL

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

公开(公告)号：US20190279806A1

公开(公告)日：2019-09-12

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Sandeep GAAN ,  Sri Ranga Sai BOYAPATI ,  Prithwish CHATTERJEE ,  Sameer PAITAL ,  Rahul JAIN ,  Junnan ZHAO

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US20190206767A1

公开(公告)日：2019-07-04

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

CPC classification number: H01L23/485 ,  H01L21/0275 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54426 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02372

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.