45.
    发明专利
    未知

    公开(公告)号:MX173763B

    公开(公告)日:1994-03-25

    申请号:MX9102603

    申请日:1991-12-17

    Applicant: MOTOROLA INC

    Abstract: The pi /4-QPSK coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The pi /4-QPSK coherent detector recovers bursts of data, in a TDMA system, that has been encoded in an amplitude modulated vector's phase angle. The pi /4-QPSK coherent detector detects the pi /4-QPSK constellation of the incoming modulated signal and outputs the recovered data stream.

    Apparatus and method for recovering a time-varying signal using multiple sampling points

    公开(公告)号:GB2265800A

    公开(公告)日:1993-10-06

    申请号:GB9310866

    申请日:1992-08-19

    Applicant: MOTOROLA INC

    Abstract: The present invention presents an apparatus and method for recovering symbols in a data packet (101) transmitted to a receiver from a remote signal source (204) in a time-varying channel using multiple sampling points. In a digital cellular radiotelephone TDMA system, the receiver (202) performs a complex correlation on the desired slot sync word (DSSW) and the coded digital verification color code (CDVCC) in the data packet (101) and on the adjacent slot sync word (ASSW) in an adjacent data packet (102) to produce a first, second and third optimum sampling point, respectively. The data packet (101) is divided into four regions (A, B, C and D). The symbols in each region (A, B, C and D) are serially recovered using one or more of the multiple sampling points depending on the quality of the sampling point adjacent to each region (A, B, C and D).

    50.
    发明专利
    未知

    公开(公告)号:BR9900169A

    公开(公告)日:2000-01-11

    申请号:BR9900169

    申请日:1999-01-26

    Applicant: MOTOROLA INC

    Abstract: According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

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