Method and apparatus for vector signal processing

    公开(公告)号:AU2006317657A1

    公开(公告)日:2007-05-31

    申请号:AU2006317657

    申请日:2006-10-09

    Applicant: MOTOROLA INC

    Abstract: A vector signal processor ( 80 ) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) ( 82 ), a mixer, or other phase shifter ( 70 ) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

    System and method for providing an input to a distributed power amplifying system

    公开(公告)号:AU2006246355A1

    公开(公告)日:2006-11-16

    申请号:AU2006246355

    申请日:2006-04-27

    Applicant: MOTOROLA INC

    Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections ( 102, 104, 106 , and 108 ) and a plurality of drivers ( 110, 112, 114 , and 116 ). Each of the plurality of drivers receives a common transmit signal ( 118 ) and an individual control signal ( 120, 122, 124 , and 126 ). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal ( 128, 130, 132 , and 134 ) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

    Adjustable frequency delay-locked loop

    公开(公告)号:AU2005241876A1

    公开(公告)日:2005-11-17

    申请号:AU2005241876

    申请日:2005-03-14

    Applicant: MOTOROLA INC

    Abstract: A delay-locked loop 300 that includes: an adjustable frequency source ( 320 ) for generating a clock signal ( 322 ) having an adjustable frequency; an adjustment and tap selection controller ( 310 ) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line ( 330 ) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit ( 370 ) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

    Cascaded delay locked loop circuit
    46.
    发明专利

    公开(公告)号:HK1069025A1

    公开(公告)日:2005-05-06

    申请号:HK05101153

    申请日:2005-02-12

    Applicant: MOTOROLA INC

    Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.

    50.
    发明专利
    未知

    公开(公告)号:DK0587792T3

    公开(公告)日:1999-06-07

    申请号:DK92913963

    申请日:1992-06-02

    Applicant: MOTOROLA INC

    Abstract: A communication device 200 capable of operating in a communication system 100 having a control system which generates information signals with redundant information is disclosed. The communication device comprises: a receiver 214 for receiving the information signals; a circuit which can determine the signal quality of the received information signals 234; and a controller 226 which decodes the received information signals, and further compares the signal quality of the information signals with a predetermined value, and decides if the received signal quality is at least equal to the predetermined value in order to only decode a portion of the information signal. Upon the communication device decoding a portion of the information signal, the communication device 200 is placed in a battery saving mode in order to conserve battery life.

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