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22 records (took 0.023 seconds)

    1.
    发明专利
    未知

    公开(公告)号：FI943662A0

    公开(公告)日：1994-08-05

    申请号：FI943662

    申请日：1994-08-05

    Applicant: MOTOROLA INC

    Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

    IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H01L

    Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

    Interconnection Structure for Crosstalk Reduction to Improve Off-Chip Selectivity
    3.
    发明专利
    Interconnection Structure for Crosstalk Reduction to Improve Off-Chip Selectivity 未知

    公开(公告)号：CA2130225A1

    公开(公告)日：1995-03-01

    申请号：CA2130225

    申请日：1994-08-16

    Applicant: MOTOROLA INC

    Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

    IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H01L23/538

    Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

    4.
    发明专利
    未知

    公开(公告)号：AT349809T

    公开(公告)日：2007-01-15

    申请号：AT02773869

    申请日：2002-10-23

    Applicant: MOTOROLA INC

    Inventor： JUAN JUI-KUO ,  STENGEL ROBERT E ,  MARTIN FREDERICK L ,  BOCKELMAN DAVID E

    IPC: H03L7/07 ,  H03L7/081 ,  H03L7/14 ,  H03L7/16 ,  H03H11/26

    Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.

    Apparatus and method for generating accurate quadrature over a frequency range
    5.
    发明专利
    Apparatus and method for generating accurate quadrature over a frequency range 未知

    公开(公告)号：AU3668301A

    公开(公告)日：2001-09-03

    申请号：AU3668301

    申请日：2001-02-05

    Applicant: MOTOROLA INC

    Inventor： STENGEL ROBERT ,  BOCKELMAN DAVID E ,  BRUESKE DANIEL E

    IPC: H03H11/16 ,  H03K3/00

    Abstract: The invention produces an accurate quadrature relationship for a range of frequencies using passive components in the primary quadrature splitting circuits. A reference oscillator (202) generates a reference signal which is fed to a conventional passive quadrature splitter circuit (204). However, since the reference circuit provides signals over a range of frequencies, the output signals of the passive quadrature splitter may not have an accurate quadrature relationship. The output signals of the passive quadrature splitter are then equalized in magnitude, and the sum and difference of the signals are produced, which will be in an accurate quadrature relationship.

    Interconnection structure for crosstalk reduction to improve off-chip selectivity
    6.
    发明专利
    Interconnection structure for crosstalk reduction to improve off-chip selectivity 未知

    公开(公告)号：ZA946141B

    公开(公告)日：1995-11-08

    申请号：ZA946141

    申请日：1994-08-15

    Applicant: MOTOROLA INC

    Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

    IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H01R ,  H05K ,  H01P

    Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

    Interconnection structure for crosstalk reduction to improve off-chip selectivity
    7.
    发明专利
    Interconnection structure for crosstalk reduction to improve off-chip selectivity 未知

    公开(公告)号：AU6734894A

    公开(公告)日：1995-03-16

    申请号：AU6734894

    申请日：1994-07-08

    Applicant: MOTOROLA INC

    Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

    IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H03F3/195 ,  H04B1/16 ,  H01L27/04

    Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

    Repetidor inteligente y método de proporcionar señalización incrementada
    8.
    发明专利
    Repetidor inteligente y método de proporcionar señalización incrementada 未知

    公开(公告)号：ES2426962T3

    公开(公告)日：2013-10-28

    申请号：ES02709333

    申请日：2002-02-04

    Applicant: MOTOROLA INC ,  MOTOROLA MOBILITY LLC

    Inventor： BOCKELMAN DAVID E ,  OOI LENG H

    IPC: H04B7/15

    Abstract: Un sistema para proporcionar señalización incrementada en un sistema de comunicaciones (10), incluyendo: un sistema repetidor (12) operable para recibir y almacenar datos característicos operativos (130) procedentes deuna unidad de comunicaciones iniciante (14) que ha establecido una llamada a una o más unidades decomunicaciones (16, 18), caracterizándose el sistema porque el sistema repetidor (12) está dispuesto para transmitir al menos algunos de los datos característicos operativosalmacenados durante una interrupción detectada en la transmisión de la llamada establecida de la unidad decomunicaciones iniciante (14) a una o más unidades de comunicaciones (16, 18).

    Cascaded delay locked loop circuit
    9.
    发明专利
    Cascaded delay locked loop circuit 未知

    公开(公告)号：HK1069025A1

    公开(公告)日：2005-05-06

    申请号：HK05101153

    申请日：2005-02-12

    Applicant: MOTOROLA INC

    Inventor： JUAN JUI-KUO ,  STENGEL ROBERT E ,  MARTIN FREDERICK L ,  BOCKELMAN DAVID E

    IPC: H03L20060101 ,  H03H20060101 ,  H03L7/07 ,  H03L7/081 ,  H03L7/14 ,  H03L7/16

    Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.

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