公开(公告)号：WO02061519A2

公开(公告)日：2002-08-08

申请号：PCT/US0203012

申请日：2002-01-30

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  GOLDBLATT JEREMY

IPC: G05F3/26 ,  G05F3/20 ,  H03F3/45

CPC classification number: G05F3/205

Abstract: A bias circuit (126) is described for use in biasing an operational amplifier (110) to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. The bias circuit (126) includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit (136) for developing an equivalent resistance between the current source devices. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operation amplifier being biased. When employed in connection with operationa amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variation. Furthermore, by positioning the resistance quivalent circuit (136) between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations.

Abstract translation: 描述偏置电路（126）用于偏置运算放大器（110），以保持恒定的跨导除以负载电容（即，恒定的gm / CL），尽管温度和工艺变化以及身体效应。 偏置电路（126）包括一对电流源装置和用于在电流源装置之间产生等效电阻的开关电容器（SC）等效电阻器电路（136）。 通过提供由非重叠固定时钟信号时钟的SC等效电阻电路，偏置电路的gm / CL保持基本恒定。 因此，在被偏置的运算放大器内维持固定带宽。 当与SC电路的放大器连接使用时，恒定带宽使得SC电路能够以恒定的开关速度工作，尽管温度和工艺变化。 此外，通过将电阻等效电路（136）定位在偏置电路的电流源装置之间，消除源之间的电压差，从而消除任何阈值电压失配，从而补偿体效应变化。

公开(公告)号：WO2009111500A2

公开(公告)日：2009-09-11

申请号：PCT/US2009035917

申请日：2009-03-03

Applicant: QUALCOMM INC ,  BAZARJANI SEYFOLLAH ,  MIAO GUOQING ,  FITZGERALD JOSEPH R ,  KULKARNI PRAJAKT V ,  GAGNE JUSTIN JOSEPH ROSEN ,  MCALLISTER GENE H ,  HINRICHS JEFFREY ,  VAN DER WAGT JAN PAUL

Inventor： BAZARJANI SEYFOLLAH ,  MIAO GUOQING ,  FITZGERALD JOSEPH R ,  KULKARNI PRAJAKT V ,  GAGNE JUSTIN JOSEPH ROSEN ,  MCALLISTER GENE H ,  HINRICHS JEFFREY ,  VAN DER WAGT JAN PAUL

IPC: H03M1/06

CPC classification number: H03F1/0222 ,  H03F1/0211 ,  H03F2200/03 ,  H03G3/30 ,  H03G3/3005 ,  H03G3/32

Abstract: A system and method of improving the efficiency in the power consumption of an audio system. In essence, the technique is to adjust the power delivered from the power supply to the analog section, such as the power amplifier, in response to the volume level indicated by the volume control module and/or in response to the detected characteristic of the input audio signal. Thus, in this manner, the analog section is operated in a manner that is related to the level of the signal it is processing. Additionally, the system and method also relate to a technique of adjusting the dynamic ranges of the digital signal and the analog signal to improve the overall dynamic range of the system without needing to consume additional power.

Abstract translation: 提高音频系统功耗效率的系统和方法。 本质上，该技术是响应于由音量控制模块指示的音量水平和/或响应于所检测到的输入特性而调整从电源传送到诸如功率放大器的模拟部分的功率 音频信号。 因此，以这种方式，模拟部分以与其正在处理的信号的电平有关的方式进行操作。 此外，该系统和方法还涉及调整数字信号和模拟信号的动态范围以提高系统的整体动态范围而不需要消耗额外功率的技术。

公开(公告)号：WO2004004120A3

公开(公告)日：2004-09-23

申请号：PCT/US0320403

申请日：2003-06-26

Applicant: QUALCOMM INC

Inventor： KEEHR EDWARD ,  WANG SEAN ,  BAZARJANI SEYFOLLAH

IPC: H03H19/00 ,  H03M3/00

CPC classification number: H03H19/004 ,  H03M3/344 ,  H03M3/502

Abstract: Switched-capacitor filter for filtering the output signal of a digital-to-analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital-to-analog converter augmented with DCT and correlated double sampling (CDS) techniques. A digital to analog converter augmented with Postfilter Droop Compensation. In one embodiment, an electronic system includes a digital-to-analog converter (DAC) having a DAC output (Vin); and an analog postfilter having a postfilter input coupled to the DAC output; said analog postfilter (300) including a first direct charge transfer coupled filter said postfilter employing the CDS technique.

Abstract translation: 用于对直流电荷转换（DCT）技术进行增益的数/模转换器的输出信号进行滤波的开关电容滤波器。 数字 - 模拟转换器增强了DCT和相关双采样（CDS）技术。 数字到模拟转换器通过后置滤波器下垂补偿增强。 在一个实施例中，电子系统包括具有DAC输出（Vin）的数模转换器（DAC）; 以及具有耦合到DAC输出的后滤波器输入的模拟后滤波器; 所述模拟后置滤波器（300）包括采用所述CDS技术的所述后置滤波器的第一直接电荷转移耦合滤波器。

公开(公告)号：WO0237686A3

公开(公告)日：2004-02-19

申请号：PCT/US0146188

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  WANG SEAN ,  PELUSO VINCENZO

IPC: H03M3/02

CPC classification number: H03M3/32 ,  H03M3/394 ,  H03M3/406 ,  H03M3/418 ,  H03M3/47

Abstract: A control mechanism that can be used to control a SIGMA DELTA to provide the required level of performance while reducing power consumption. The SIGMA DELTA ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMA DELTA ADC that is similar to the SIGMA DELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMA DELTA stages in the SIGMA DELTA ADC.

Abstract translation: 一种可用于控制SIGMA DELTA以提供所需性能水平同时降低功耗的控制机制。 SIGMA DELTA ADC设计为多级（即，环路或部分），并且随着更多级的启用，提供改进的性能（例如，更高的动态范围）。 控制机构选择性地实现足够数量的级以提供所需性能并且禁用剩余级以节省功率。 控制机制通过测量信号路径上类似于SIGMA DELTA ADC的SIGMA DELTA ADC的ADC输入信号的一个或多个特性（例如，信号电平）来实现这一点，将测量特性与特定阈值进行比较 级别，并控制阶段以达到所需目标。 在一个实现中，控制电路包括一个或多个检测器级，调理电路和信号处理器。 检测器级接收输入信号并提供检测信号。 调理电路接收检测到的信号并提供条件样本。 信号处理器接收经调节的样本并提供选择性地禁用SIGMA DELTA ADC中的零个或更多个SIGMA DELTA级的控制信号。

公开(公告)号：WO0223734A3

公开(公告)日：2003-09-12

申请号：PCT/US0129119

申请日：2001-09-18

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH

IPC: H03M3/02

CPC classification number: H03M3/47 ,  H03M3/406 ,  H03M3/418 ,  H03M3/43 ,  H03M3/454

Abstract: A bandpass SIGMA DELTA ADC utilizing either a single-loop or a MASH architecure wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

Abstract translation: 利用单回路或MASH结构的带通SIGMA DELTA ADC，其中谐振器被实现为延迟单元谐振器，基于延迟单元的谐振器，前向欧拉谐振器，双路交织谐振器或四路交错谐振器， 路径交织谐振器。 谐振器可以用诸如有源RC，gm-C，MOSFET-C，开关电容器或开关电流的模拟电路技术来合成。 开关电容器或开关电流电路可以使用单采样，双采样或多采样电路进行设计。 使用开关电容电路的SIGMA DELTA ADC的非严格要求允许ADC以CMOS工艺实现，以最大限度地降低成本并降低功耗。 双采样电路提供了改进的匹配和改进的采样时钟抖动容限。 特别地，带通MASH 4-4 SIGMA DELTA ADC在CDMA应用的过采样比为32时提供85dB的模拟信噪比。 带通SIGMA DELTA ADC也可与欠采样一起使用，以提供频率下变频。

公开(公告)号：WO02069613A3

公开(公告)日：2003-05-22

申请号：PCT/US0205328

申请日：2002-02-22

Applicant: QUALCOMM INC

Inventor： OLIVEIRA LOUIS D ,  GUPTA SAMIR KUMAR ,  BAZARJANI SEYFOLLAH ,  SU WENJUN

IPC: H03G7/00 ,  H03M1/70 ,  H04M1/73 ,  H04M1/60

CPC classification number: H03G7/007 ,  H03M1/70

Abstract: A wireless communication device (100) may include a receiver (110), a memory (104), a digital-to-analog converter (128) an audio playback system (124) and other features. A dynamic range controller (130) selectively generates control signals to adjust, at least in part, the operational dynamic range of the digital to analog converter (128) for digital signals received by the receiver (110) or stored in the memory (104). The selection of dynamic range is based on identifying a characteristic. In one embodiment, the control signals are used to selectively operate the digital-to analog converter (128) at a particular dynamic range based on a sampling rate of a received digital audio signal.

Abstract translation: 无线通信设备（100）可以包括接收机（110），存储器（104），数模转换器（128）音频回放系统（124）和其他特征。 动态范围控制器（130）选择性地产生控制信号，以至少部分地调整用于由接收器（110）接收或存储在存储器（104）中的数字信号的数模转换器（128）的操作动态范围， 。 动态范围的选择基于识别特征。 在一个实施例中，控制信号用于基于所接收的数字音频信号的采样率在特定动态范围内有选择地操作数模转换器（128）。