公开(公告)号：AU2015333890B2

公开(公告)日：2019-03-21

申请号：AU2015333890

申请日：2015-10-06

Applicant: QUALCOMM INC

Inventor： ANG PETER PUI LOK ,  BURKE JOSEPH PATRICK ,  JI TINGFANG ,  BHUSHAN NAGA ,  MUKKAVILLI KRISHNA KIRAN ,  HOWARD MICHAEL ALEXANDER ,  SMEE JOHN EDWARD ,  SORIAGA JOSEPH BINAMIRA

IPC: H04W52/26

Abstract: Methods, systems, and devices are described for wireless communication. A first device, such as a user equipment (UE) may be configured with a peak data rate that corresponds to the radio frequency (RF) capacity of a modem and a sustained data rate that corresponds to the baseband capacity. The first device may receive a set of data blocks during a transmission burst from a second device. The quantity of data blocks in the burst may be based on the peak data rate. The first device may store time domain samples or frequency tones for the data and then power down the RF components for an interval based on how long it will take to process the data. The first device may then process the data at the sustained data rate. After the rest interval, the first device may power up the RF components and receive another burst of data.

公开(公告)号：AU2016280523A1

公开(公告)日：2017-11-23

申请号：AU2016280523

申请日：2016-05-20

Applicant: QUALCOMM INC

Inventor： SHELLHAMMER STEPHEN JAY ,  ANG PETER PUI LOK ,  BURKE JOSEPH PATRICK ,  JI TINGFANG ,  NGUYEN CONG ,  SORIAGA JOSEPH BINAMIRA

IPC: H04W52/02 ,  H04L5/00 ,  H04L27/00 ,  H04L27/26

Abstract: When embedding a signal into a selected subcarrier of a multicarrier downlink waveform of regular data/control signaling, a base station modulates the embedded signal with a different modulation scheme than the other data in the downlink waveform. The base station nulls adjacent subcarriers to minimize interference at a low-power wake-up receiver of an IOE device(s). The IOE device wakes up the low-power wake-up receiver at scheduled times to listen for the signal. For synchronization signals, the IOE device corrects a local clock based on a correlation value of the signal to a predetermined sequence. For wake-up signals, the IOE device correlates whatever is detected at the antenna to a predetermined sequence and compares the correlation value to a predetermined threshold. If the threshold is met, the IOE device registers a wake-up signal and wakes the primary transceiver of the device. If not, the receiver goes back to sleep.

公开(公告)号：CO2017004048A2

公开(公告)日：2017-08-31

申请号：CO2017004048

申请日：2017-04-26

Applicant: QUALCOMM INC

Inventor： JI TINGFANG ,  SMEE JOHN EDWARD ,  BHUSHAN NAGA ,  MUKKAVILLI KRISHNA KIRAN ,  ANG PETER PUI LOK ,  BURKE JOSEPH PATRICK ,  SORIAGA JOSEPH BINAMIRA

IPC: H04W52/02

Abstract: Se revelan sistemas, métodos, aparatos y productos de programas para computadora para realizar conmutación dinámica del ancho de bandaentre señales de control y señales de datos de diferentes anchos de banda.Se revelan formatos de trama en donde las señales de control se transmiten en diferentesanchos de bandaa las señales de datos.Se revelan arquitecturas de receptores para recibir formatos de señalización.Un receptor puede recibir una señal de control de banda relativamente estrecha mientras consume una energía relativamente bajay luego se ajustan dinámicamente las características de diversos componentes para recibir una señal de datos con un mayor ancho de bandamientras consume una energía relativamente mayor.

公开(公告)号：CA2962741A1

公开(公告)日：2016-05-06

申请号：CA2962741

申请日：2015-09-05

Applicant: QUALCOMM INC

Inventor： ANG PETER PUI LOK ,  BURKE JOSEPH PATRICK ,  JI TINGFANG ,  BHUSHAN NAGA ,  MUKKAVILLI KRISHNA KIRAN ,  SORIAGA JOSEPH BINAMIRA ,  SMEE JOHN EDWARD

IPC: H04W72/12 ,  H04W52/02

Abstract: Systems, methods, apparatuses, and computer-program products for performing dynamic bandwidth switching between control signals and data signals of differing bandwidths are disclosed. Frame formats are disclosed in which control signals are transmitted at different bandwidths than data signals. Receiver architectures for receiving the signaling formats are disclosed. A receiver can receive a relatively narrowband control signal while consuming a relatively low power and then dynamically adjust characteristics of various components to receive a data signal at a higher bandwidth while consuming a relatively higher power.

公开(公告)号：AR046488A1

公开(公告)日：2005-12-14

申请号：ARP040101397

申请日：2004-04-23

Applicant: QUALCOMM INC

Inventor： BURKE JOSEPH PATRICK

IPC: H03M1/06 ,  H03M1/66 ,  H03M3/00 ,  H04B1/69 ,  H04L27/04

Abstract: Un circuito electrónico para procesar una senal digital pueden incluir una pluralidad de circuitos de retardo digital, estando cada uno de ellos configurado para producir una réplica retardada de la senal digital; una pluralidad de convertidores digital-analógico, estando cada uno de ellos configurado para convertir la senal digital o la réplica retardada desde uno de los circuitos de retardo, en una senal analógica; una pluralidad de circuitos de ganancia analógica, estando cada uno de ellos configurado para ajustar la senal analógica desde uno de los convertidores digital-analógico mediante un factor de ganancia, y teniendo cada uno de ellos una salida; y un sumador analógico configurado para sumar las salidas de los circuitos de ganancia analógica. La cantidad de circuitos de retardo y la magnitud de los retardos y ganancias pueden ser seleccionadas para hacer que el circuito funcione como un filtro de paso de banda, un filtro de paso alto, un filtro de paso bajo, un filtro de muesca, o cualquier otro tipo de filtro. El circuito puede ser utilizado en una amplia variedad de aplicaciones que incluyen un transceptor (tal como una estación abonada) y en aplicaciones de banda ultra ancha.

公开(公告)号：WO2007104027A2

公开(公告)日：2007-09-13

申请号：PCT/US2007063603

申请日：2007-03-08

Applicant: QUALCOMM INC ,  SEVERSON MATTHEW LEVI ,  BURKE JOSEPH PATRICK ,  POTTIER PHILIP

Inventor： SEVERSON MATTHEW LEVI ,  BURKE JOSEPH PATRICK ,  POTTIER PHILIP

IPC: G06F11/36

CPC classification number: G06F11/3656

Abstract: A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is determined to be associated with a power collapse event. A debug state of the processor is restored by loading debug registers within the processor during the execution mode.

Abstract translation: 提供了在电源崩溃之后在处理器上执行调试操作的方法。 在处理器的执行模式期间检测处理器的空闲状态。 空闲状态被确定为与功率崩溃事件相关联。 在执行模式期间，通过在处理器中加载调试寄存器来恢复处理器的调试状态。

公开(公告)号：EP1623504A4

公开(公告)日：2006-08-23

申请号：EP04760349

申请日：2004-04-23

Applicant: QUALCOMM INC

Inventor： BURKE JOSEPH PATRICK

IPC: H04B1/69 ,  H03M1/06 ,  H03M1/66 ,  H03M3/00

CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M3/504 ,  H04B1/71635

Abstract: An electronic circuit for processing a digital signal may include a plurality of digital delay circuits, each configured to produce a delayed replica of the digital signal; a plurality of digital-to-analog converters, each configured to convert the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits, each configured to adjust the analog signal from one of the digital-to-analog converters by a gain factor and each having an output; and an analog summer configured to sum the outputs of the analog gain circuits. The number of delay circuits and the magnitude of the delays and gains may be selected to cause the circuit to function as a band pass filter, a high pass filter, a low-pass filter, a notch filter, or any other type of filter. The circuit may be used in a broad variety of applications, including a transceiver (such as a subscriber station) and in ultra wideband applications.

Abstract translation: 用于处理数字信号的电子电路可以包括多个数字延迟电路，每个数字延迟电路被配置为产生数字信号的延迟复制品; 多个数模转换器，每个转换器被配置为将数字信号或延迟复制品从延迟电路之一转换为模拟信号; 多个模拟增益电路，每个模拟增益电路被配置为通过增益因子调整来自所述数模转换器之一的模拟信号，并且每个具有输出; 以及模拟加法器，其被配置为对模拟增益电路的输出求和。 可以选择延迟电路的数量和延迟和增益的大小以使电路用作带通滤波器，高通滤波器，低通滤波器，陷波滤波器或任何其它类型的滤波器。 该电路可以用于广泛的应用中，包括收发器（例如用户站）和超宽带应用。

公开(公告)号：WO2005071906A3

公开(公告)日：2005-10-20

申请号：PCT/US2005000401

申请日：2005-01-07

Applicant: QUALCOMM INC ,  KRISHNAN RANGANATHAN ,  BURKE JOSEPH PATRICK ,  RAJKOTIA AMOL ,  NANDA SANJIV

Inventor： KRISHNAN RANGANATHAN ,  BURKE JOSEPH PATRICK ,  RAJKOTIA AMOL ,  NANDA SANJIV

IPC: H04B7/26 ,  H04L12/56

CPC classification number: H04W72/1231 ,  H04W84/18

Abstract: Systems and techniques are disclosed relating to wireless communications. The systems and techniques involve wireless communications wherein a process, module or communications terminal schedules communications over a frame having a plurality of time slots. The process, module or communications terminal may be used to assign information to be transmitted between two terminals to a block of the time slots within a frame, and reordering the time slot assignments within the frame using a permutation function, the permutation function being a function of frame count.

Abstract translation: 公开了与无线通信有关的系统和技术。 该系统和技术涉及无线通信，其中过程，模块或通信终端在具有多个时隙的帧上调度通信。 过程，模块或通信终端可以用于将要在两个终端之间传输的信息分配给帧内的时隙的块，并且使用置换函数对帧内的时隙分配进行重新排序，置换函数是函数 帧数。

公开(公告)号：WO2004098062A3

公开(公告)日：2005-08-11

申请号：PCT/US2004012577

申请日：2004-04-23

Applicant: QUALCOMM INC ,  BURKE JOSEPH PATRICK

Inventor： BURKE JOSEPH PATRICK

IPC: H03M1/06 ,  H03M1/66 ,  H03M3/00 ,  H04B1/69 ,  H04L27/04

CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M3/504 ,  H04B1/71635

Abstract: An electronic circuit for processing a digital signal may include a plurality of digital delay circuits, each configured to produce a delayed replica of the digital signal; a plurality of digital-to-analog converters, each configured to convert the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits, each configured to adjust the analog signal from one of the digital-to-analog converters by a gain factor and each having an output; and an analog summer configured to sum the outputs of the analog gain circuits. The number of delay circuits and the magnitude of the delays and gains may be selected to cause the circuit to function as a band pass filter, a high pass filter, a low-pass filter, a notch filter, or any other type of filter. The circuit may be used in a broad variety of applications, including a transceiver (such as a subscriber station) and in ultra wideband applications.

Abstract translation: 用于处理数字信号的电子电路可以包括多个数字延迟电路，每个数字延迟电路被配置为产生数字信号的延迟复制品; 多个数模转换器，每个转换器被配置为将数字信号或延迟的副本从其中一个延迟电路转换为模拟信号; 多个模拟增益电路，每个模拟增益电路被配置为通过增益因子调整来自所述数模转换器之一的模拟信号，并且每个具有输出; 以及模拟加法器，其被配置为对模拟增益电路的输出求和。 可以选择延迟电路的数量和延迟和增益的大小，以使电路用作带通滤波器，高通滤波器，低通滤波器，陷波滤波器或任何其它类型的滤波器。 该电路可以用于广泛的应用中，包括收发器（例如用户台）和超宽带应用。

公开(公告)号：WO2011020070A2

公开(公告)日：2011-02-17

申请号：PCT/US2010045535

申请日：2010-08-13

Applicant: QUALCOMM INC ,  FAGG RUSSELL JOHN ,  BURKE JOSEPH PATRICK

Inventor： FAGG RUSSELL JOHN ,  BURKE JOSEPH PATRICK

IPC: H03H15/00

CPC classification number: H03H19/004 ,  H03H15/023 ,  H03H17/0657 ,  H03H17/0664

Abstract: A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.

Abstract translation: 描述了具有各种优点的离散时间（DT）低通滤波器。 在示例性设计中，DT低通滤波器包括抽取DT滤波器（其可以包括无源DT FIR滤波器和/或无源DT IIR滤波器）和有源DT滤波器。 抽取DT滤波器以第一采样率接收第一DT信号，对第一DT信号进行滤波和抽取因子N，并以低于第一采样率的第二采样速率提供第二DT信号。 N可能大于1。 有源DT滤波器对第二DT信号进行滤波，并以第二采样率提供第三DT信号。 采样器采样连续时间信号并提供第一个DT信号。 采样器可以相对于连续时间信号的电压进一步使第一DT信号的电压加倍。